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| hcs12 microcontrollers freescale.com mc9s12k family device user guide covers MC9S12KT256, mc9s12kg256, mc9s12kg128, mc9s12kl128, mc9s12kc128, mc9s12kg64, mc9s12kl64, mc9s12kc64 and mc9s12kg32 9s12kt256dgv1/d v01.09 9 sep 2004
device user guide ?9s12kt256dgv1/d v01.09 2 freescale semiconductor revision history version number revision date author description of changes 01.00 16 jul 02 original version. 01.01 22 nov 02 change load cap value on vdd and vddpll. correct expanded bus timing from 20mhz to 25 mhz. 01.02 15 jan 03 move atd interrupt vector from $ffd0 to $ffd2. change pweh and tdsw parameter in external bus timing. 01.03 13 jun 03 expand to a k-family soc guide and include 9s12kt256. 01.04 18 jun 03 replace 16-channel atd with two 8-channel atds for 9s12kt256. 01.05 14 nov 03 changed to a device user guide and added document number. updated table a-17 oscillator characteristics. replaced xclks with pe7 for clock selection diagrams. added ctrl to table 2-1 signal properties. replaced burst programming with row programming in nvm electricals. changed digital logic to internal logic. added lrae bootloader information. changed pw el , pw eh , t dsw , t acce , t nad , t nav , t rwv , t lsv , t nov , t p0v and t p1v in the external bus timing. added voltage regulator characteristics. 01.06 10 feb 04 updated table a-7 3.3v i/o characteristics. 01.07 13 may 04 updated table a-16 nvm timing characteristics. corrected a.6.1.2 row programming time t bwpgm equation 01.08 20 jul 04 expanded k-family to include 9s12kc128, 9s12kc64, 9s12kl128 and 9s12kl64. 01.09 9 sep 04 updated osciilator start up time and supply current characteristics. added atdctl0 and atdctl1 register bits to sec 1.7. device user guide ?9s12kt256dgv1/d v01.09 3 freescale semiconductor table of contents section 1 introduction 1.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4 mc9s12kg(l)(c)128(64)(32) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.5 mc9s12kt(g)256 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.6 device memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.7 detailed register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.8 part id assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 section 2 signal description 2.1 device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.2 signal properties summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.1 extal, xtal ?oscillator pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.2 reset ?external reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.3 test ?test pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.4 vregen ?voltage regulator enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.3.5 xfc ?pll loop filter pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.6 bkgd / taghi / modc ?background debug, tag high, and mode pin . . . . . 61 2.3.7 pad[15:8] / an[15:8] ?port ad input pins [15:8]. . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.8 pad[7:0] / an[7:0] ?port ad input pins [7:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.9 pa[7:0] / addr[15:8] / data[15:8] ?port a i/o pins . . . . . . . . . . . . . . . . . . . . 61 2.3.10 pb[7:0] / addr[7:0] / data[7:0] ?port b i/o pins . . . . . . . . . . . . . . . . . . . . . . 62 2.3.11 pe7 / noacc / xclks ?port e i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.12 pe6 / modb / ipipe1 ?port e i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.13 pe5 / moda / ipipe0 ?port e i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.14 pe4 / eclk ?port e i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 2.3.15 pe3 / lstrb / taglo ?port e i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.16 pe2 / r/w ?port e i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.17 pe1 / irq ?port e input pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.18 pe0 / xirq ?port e input pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.19 ph7 / kwh7 / ss2 ?port h i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 device user guide ?9s12kt256dgv1/d v01.09 4 freescale semiconductor 2.3.20 ph6 / kwh6 / sck2 ?port h i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.21 ph5 / kwh5 / mosi2 ?port h i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.22 ph4 / kwh4 / miso2 ?port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.23 ph3 / kwh3 / ss1 ?port h i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.24 ph2 / kwh2 / sck1 ?port h i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.25 ph1 / kwh1 / mosi1 ?port h i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.26 ph0 / kwh0 / miso1 ?port h i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.27 pj7 / kwj7 / txcan4 / scl ?port j i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.28 pj6 / kwj6 / rxcan4 / sda ?port j i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.29 pj[1:0] / kwj[1:0] ?port j i/o pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.30 pk7 / ecs / romctl ?port k i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 2.3.31 pk[5:0] / xaddr[19:14] ?port k i/o pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.32 pm7 / txcan4 ?port m i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.33 pm6 / rxcan4 ?port m i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.34 pm5 / txcan0 / txcan4 / sck0 ?port m i/o pin 5 . . . . . . . . . . . . . . . . . . . . 66 2.3.35 pm4 / rxcan0 / rxcan4/ mosi0 ?port m i/o pin 4 . . . . . . . . . . . . . . . . . . . 66 2.3.36 pm3 / txcan1 / txcan0 / ss0 ?port m i/o pin 3 . . . . . . . . . . . . . . . . . . . . . 67 2.3.37 pm2 / rxcan1 / rxcan0 / miso0 ?port m i/o pin 2 . . . . . . . . . . . . . . . . . . . 67 2.3.38 pm1 / txcan0 ?port m i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.39 pm0 / rxcan0 ?port m i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.40 pp7 / kwp7 / pwm7 / sck2 ?port p i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.41 pp6 / kwp6 / pwm6 / ss2 ?port p i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.42 pp5 / kwp5 / pwm5 / mosi2 ?port p i/o pin 5. . . . . . . . . . . . . . . . . . . . . . . . 67 2.3.43 pp4 / kwp4 / pwm4 / miso2 ?port p i/o pin 4. . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.44 pp3 / kwp3 / pwm3 / ss1 ?port p i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.45 pp2 / kwp2 / pwm2 / sck1 ?port p i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.46 pp1 / kwp1 / pwm1 / mosi1 ?port p i/o pin 1. . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.47 pp0 / kwp0 / pwm0 / miso1 ?port p i/o pin 0. . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.48 ps7 / ss0 ?port s i/o pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.49 ps6 / sck0 ?port s i/o pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.50 ps5 / mosi0 ?port s i/o pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.51 ps4 / miso0 ?port s i/o pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.52 ps3 / txd1 ?port s i/o pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.53 ps2 / rxd1 ?port s i/o pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.54 ps1 / txd0 ?port s i/o pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.3.55 ps0 / rxd0 ?port s i/o pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 device user guide ?9s12kt256dgv1/d v01.09 5 freescale semiconductor 2.3.56 pt[7:0] / ioc[7:0] ?port t i/o pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.4 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 2.4.1 vddx,vssx ?power supply pins for i/o drivers . . . . . . . . . . . . . . . . . . . . . . . 70 2.4.2 vddr, vssr ?power supply pins for i/o drivers & for internal voltage regulator 70 2.4.3 vdd1, vdd2, vss1, vss2 ?power supply pins for internal logic . . . . . . . . . 70 2.4.4 vdda, vssa ?power supply pins for atd and vreg . . . . . . . . . . . . . . . . . . 70 2.4.5 vrh, vrl ?atd reference voltage input pins . . . . . . . . . . . . . . . . . . . . . . . . 70 2.4.6 vddpll, vsspll ?power supply pins for pll . . . . . . . . . . . . . . . . . . . . . . . . 70 section 3 system clock description section 4 modes of operation 4.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 4.2 chip configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.3 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 4.3.1 securing the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.2 operation of the secured microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.3 unsecuring the microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.4 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.4.1 stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.4.2 pseudo stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.4.3 wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.4.4 run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 section 5 resets and interrupts 5.1 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 5.2 vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.2.1 vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.3 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.1 effects of reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 section 6 hcs12 core block description 6.1 cpu12 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.2 hcs12 background debug module (bdm) block description . . . . . . . . . . . . . . . . . 78 6.3 hcs12 debug (dbg) block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.4 hcs12 interrupt (int) block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 device user guide ?9s12kt256dgv1/d v01.09 6 freescale semiconductor 6.5 hcs12 multiplexed external bus interface (mebi) block description . . . . . . . . . . . 79 6.6 hcs12 module mapping control (mmc) block description . . . . . . . . . . . . . . . . . . . 79 section 7 analog to digital converter (atd) block description section 8 clock reset generator (crg) block description 8.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 section 9 eeprom block description section 10 flash eeprom block description section 11 iic block description section 12 mscan block description section 13 osc block description section 14 port integration module (pim) block description section 15 pulse width modulator (pwm) block description section 16 serial communications interface (sci) block description section 17 serial peripheral interface (spi) block description section 18 timer (tim) block description section 19 voltage regulator (vreg) block description 19.1 device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 19.1.1 vdd1, vdd2, vss1, vss2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 appendix a electrical characteristics a.1 general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.1.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.1.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.1.3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 a.1.4 current injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 device user guide ?9s12kt256dgv1/d v01.09 7 freescale semiconductor a.1.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 a.1.6 esd protection and latch-up immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 a.1.7 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 a.1.8 power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 87 a.1.9 i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 a.1.10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 a.2 voltage regulator (vreg_3v3) operating characteristics . . . . . . . . . . . . . . . . . . . 94 a.3 chip power-up and lvi/lvr graphical explanation . . . . . . . . . . . . . . . . . . . . . . . . . 95 a.4 output loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 a.4.1 resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 a.4.2 capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 a.5 atd characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 a.5.1 atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 a.5.2 factors influencing accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 a.5.3 atd accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 a.6 nvm, flash and eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 a.6.1 nvm timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 a.6.2 nvm reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 a.7 reset, oscillator and pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 a.7.1 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 a.7.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 a.7.3 phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 a.8 mscan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 a.9 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 a.9.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 a.9.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 a.10 external bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 a.10.1 general muxed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 appendix b package information b.1 80-pin qfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 b.2 100-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 b.3 112-pin lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 device user guide ?9s12kt256dgv1/d v01.09 8 freescale semiconductor device user guide ?9s12kt256dgv1/d v01.09 9 freescale semiconductor list of figures figure 0-1 order part number coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 1-1 mc9s12kg(l)(c)128(64)(32) block diagram . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 1-2 mc9s12kt(g)256 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 1-3 MC9S12KT256 and mc9s12kg256 memory map . . . . . . . . . . . . . . . . . . . . 23 figure 1-4 mc9s12kg128, mc9s12kl128 and mc9s12kc128 memory map . . . . . . 24 figure 1-5 mc9s12kg64, mc9s12kl64 and mc9s12kc64 memory map . . . . . . . . . 25 figure 1-6 mc9s12kg32 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 2-1 pin assignments for 112 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 2-2 pin assignments for 100 lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 2-3 pin assignments for 80 qfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 2-4 pll loop filter connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 2-5 loop controlled pierce oscillator connections (pe7=1) . . . . . . . . . . . . . . . . 62 figure 2-6 full swing pierce oscillator connections (pe7=0) . . . . . . . . . . . . . . . . . . . . 63 figure 2-7 external clock connections (pe7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 3-1 clock connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure a-1 voltage regulator - chip power-up and voltage drops (not scaled) . . . . . 95 figure a-2 atd accuracy definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure a-3 basic pll functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure a-4 jitter definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure a-5 spi master timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure a-6 spi master timing (cpha =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure a-7 spi slave timing (cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure a-8 spi slave timing (cpha =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure a-9 general external bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure b-1 80-pin qfp mechanical dimensions (case no. 841b) . . . . . . . . . . . . . . . . 122 figure b-2 100-pin lqfp mechanical dimensions (case no. 983) . . . . . . . . . . . . . . . 123 figure b-3 112-pin lqfp mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . 124 device user guide ?9s12kt256dgv1/d v01.09 10 freescale semiconductor device user guide ?9s12kt256dgv1/d v01.09 11 freescale semiconductor list of tables table 0-1 list of mc9s12k-family members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 0-2 document references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 1-1 mc9s12kt(g)256 device memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 1-2 mc9s12kg(l)(c)128(64)(32) device memory map . . . . . . . . . . . . . . . . . . . . 22 table 1-3 detailed mscan foreground receive and transmit buffer layout. . . . . . . . 43 table 1-4 assigned part id numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 1-5 memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 2-1 signal properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 2-2 power and ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 2-3 clock selection based on pe7 during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 4-1 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 4-2 clock selection based on pe7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 4-3 voltage regulator vregen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 5-1 interrupt vector locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 5-2 reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table a-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table a-2 esd and latch-up test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table a-3 esd and latch-up protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 86 table a-4 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table a-5 thermal package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table a-6 5v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table a-7 3.3v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table a-8 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table a-9 vreg_3v3 - operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table a-10 voltage regulator - capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table a-11 5v atd operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table a-12 3.3v atd operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table a-13 atd electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table a-14 5v atd conversion performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table a-15 3.3v atd conversion performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table a-16 nvm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table a-17 nvm reliability characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table a-18 startup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 device user guide ?9s12kt256dgv1/d v01.09 12 freescale semiconductor table a-19 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table a-20 pll characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table a-21 mscan wake-up pulse characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table a-22 spi master mode timing characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table a-23 spi slave mode timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table a-24 expanded bus timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 device user guide ?9s12kt256dgv1/d v01.09 13 freescale semiconductor preface the device user guide provides information about the mc9s12k-family devices made up of standard hcs12 blocks and the hcs12 processor core. this document is part of the customer documentation. a complete set of device manuals also includes all the individual block guides of the implemented modules. in a effort to reduce redundancy all module specific information is located only in the respective block guide. if applicable, special implementation details of the module are given in the block description sections of this document. table 0-1 shows a feature overview of the mc9s12k-family members. table 0-1 list of mc9s12k-family members flash ram eeprom device temp options 1 notes : 1. c: ta = 85?c, f = 25mhz. v: ta=105?c, f = 25mhz. m: ta= 125?c, f = 25mhz package can sci spi iic a/d 2 2. number of channels pwm 2 tim 2 i/o 3 3. i/o is the sum of ports capable to act as digital input or output. 256k 12k 4k MC9S12KT256 c, v, m 112 lqfp 3 2 3 1 16 8 8 91 256k 12k 4k mc9s12kg256 c, v, m 112 lqfp 2 2 3 1 16 8 8 91 80 qfp 2 2 3 1 8 7 8 59 128k 8k 2k mc9s12kg128 c, v, m 112 lqfp 2 2 3 1 16 8 8 91 100 lqfp 2 2 2 1 13 7 8 79 80 qfp 2 2 2 1 8 7 8 59 64k 4k 1k mc9s12kg64 c, v, m 112 lqfp 2 2 2 1 16 8 8 91 80 qfp 2 2 2 1 8 7 8 59 32k 2k 1k mc9s12kg32 c, v, m 80 qfp 2 2 2 1 8 7 8 59 128k 6k 2k mc9s12kl128 c, v, m 112 lqfp 1 1 2 1 16 8 8 91 100 lqfp 1 1 2 1 13 7 8 79 80 qfp 1 1 2 1 8 7 8 59 64k 4k 1k mc9s12kl64 c, v, m 112 lqfp 1 1 2 1 16 8 8 91 80 qfp 1 1 2 1 8 7 8 59 128k 6k none mc9s12kc128 c, v, m 112 lqfp 1 1 2 1 16 8 8 91 100 lqfp 1 1 2 1 13 7 8 79 80 qfp 1 1 2 1 8 7 8 59 64k 4k none mc9s12kc64 c, v, m 112 lqfp 1 1 2 1 16 8 8 91 80 qfp 1 1 2 1 8 7 8 59 device user guide ?9s12kt256dgv1/d v01.09 14 freescale semiconductor figure 0-1 shows the part number coding based on the package and temperature options for the mc9s12k-family. figure 0-1 order part number coding table 0-2 shows names and versions of the referenced documents throughout the device user guide. table 0-2 document references user guide version document order number cpu12 reference manual v02 s12cpuv2/d hcs12 background debug (bdm) block guide v04 s12bdmv4/d hcs12 debug (dbg) block guide v01 s12dbgv1/d hcs12 interrupt (int) block guide v01 s12intv1/d hcs12 multiplexed expanded bus interface (mebi) block guide v03 s12mebiv3/d hcs12 module mapping control (mmc) block guide v04 s12mmcv4/d analog to digital converter: 10-bit, 16 channels (atd_10b16c) block guide v03 s12atd10b16cv3/d 1 notes : 1. block guide for mc9s12k-family except MC9S12KT256 and mc9s12kg256. analog to digital converter: 10-bit, 8 channels (atd_10b8c) block guide v03 s12atd10b8cv3/d 2 2. block guide for MC9S12KT256 and mc9s12kg256 only. clock and reset generator (crg) block guide v04 s12crgv4/d 2k byte eeprom (eets2k) block guide v01 s12eets2kv1/d (1) 4k byte eeprom (eets4k) block guide v02 s12eets4kv2/d (2) 128k byte flash with error code correction (fts128k1ecc) block guide v01 fts128k1eccv1/d (1) 256k byte flash with error code correction (fts256k2ecc) block guide v01 fts256k2eccv1/d (2) inter ic bus (iic) block guide v02 s12iicv2/d motorola scalable can (mscan) block guide v02 s12mscanv2/d oscillator loop control pierce (osc_lcp) block guide v01 s12osclcpv1/d port integration module (1) (pim_9kg128) block guide v01 s12kg128pimv1/d port integration module (2) (pim_9kt256) block guide v01 s12kt256pimv1/d pulse width modulator 8 bit 8 channel (pwm_8b8c) block guide v01 s12pwm8b6cv1/d serial communications interface (sci) block guide v02 s12sciv2/d serial peripheral interface (spi) block guide v03 s12spiv3/d timer: 16-bit, 8 channels (tim_16b8c) block guide v01 s12tim16b8cv1/d voltage regulator (vreg_3v3) block guide v01 s12vreg3v3v1/d mc9s12 kt256 c fu package option temperature option device title controller family temperature options c = -40?c to 85?c v = -40?c to 105?c m = -40?c to 125?c package options pv = 112lqfp pu = 100lqfp fu = 80qfp device user guide ?9s12kt256dgv1/d v01.09 15 freescale semiconductor section 1 introduction 1.1 overview the mc9s12k-family is a 112/100/80 pin 16-bit flash-based microcontroller family targeted for high reliability systems. members of the mc9s12k-family have an increased performance in reliability over the life of the product due to a built-in error checking and correction code (ecc) in the flash memory. the program and erase operations automatically generate six parity bits per word making ecc transparent to the user. all members of the mc9s12k-family are comprised of standard on-chip peripherals including a 16-bit central processing unit (cpu12), up to 256k bytes of flash eeprom, up to 4k bytes of eeprom, up to 12k bytes of ram, up to two asynchronous serial communications interface (sci), up to three serial peripheral interface (spi), iic-bus, an 8-channel ic/oc timer, 16-channel or two 8-channel 10-bit analog-to-digital converters (adc), an 8-channel pulse-width modulator (pwm), up to three can 2.0 a, b software compatible modules, 29 discrete digital i/o channels (port a, port b, port e and port k), and 20 discrete digital i/o lines with interrupt and wakeup capability. the mc9s12k-family has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. the inclusion of a pll circuit allows power consumption and performance to be adjusted to suit operational requirements. 1.2 features hcs12 core 16-bit hcs12 cpu i. upward compatible with m68hc11 instruction set ii. interrupt stacking and programmer? model identical to m68hc11 iii. instruction queue iv. enhanced indexed addressing mebi (multiplexed external bus interface) mmc (memory map and interface) int (interrupt controller) dbg (debugger) bdm (background debug mode) oscillator 4mhz to 16mhz frequency range pierce with amplitude loop control clock monitor device user guide ?9s12kt256dgv1/d v01.09 16 freescale semiconductor clock and reset generator (crg) phase-locked loop clock frequency multiplier self clock mode in absence of external clock cop watchdog real time interrupt (rti) memory 32k, 64k, 128k or 256k byte flash eeprom i. internal program/erase voltage generation ii. security and block protect bits iii. hamming error correction coding (ecc) 1k, 2k or 4k byte eeprom 2k, 4k, 6k, 8k or 12k byte static ram single-cycle misaligned word accesses without wait states analog-to-digital converter(s) (adc) one 16-channel module with 10-bit resolution except for MC9S12KT256 and mc9s12kg256 two 8-channel module with 10-bit resolution for MC9S12KT256 and mc9s12kg256 external conversion trigger capability 8-channel timer (tim) programmable input capture or output compare channels simple pwm mode counter modulo reset external event counting gated time accumulation 8-channel pulse width modulator (pwm) programmable period and duty cycle per channel 8-bit 8-channel or 16-bit 4-channel edge and center aligned pwm signals emergency shutdown input two or three 1m bit per second, can 2.0 a, b software compatible modules five receive and three transmit buffers flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit four separate interrupt channels for rx, tx, error and wake-up device user guide ?9s12kt256dgv1/d v01.09 17 freescale semiconductor low-pass filter wake-up function loop-back for self test operation serial interfaces two asynchronous serial communication interface (sci) three synchronous serial peripheral interface (spi) inter-ic bus (iic) internal 2.5v regulator input voltage range from 3.15v to 5.5v low power mode capability low voltage reset (lvr) and low voltage interrupt (lvi) 20 key wake up inputs rising or falling edge triggered interrupt capability digital filter to prevent short pulses from triggering interrupts programmable pull ups and pull downs operating frequency for ambient temperatures (t a - 40 c to 125 c) 50mhz equivalent to 25mhz bus speed 112-pin lqfp, 100-pin lqfp, or 80-pin qfp package i/o lines with 3.3v/5v input and drive capability 3.3v/5v a/d converter inputs 1.3 modes of operation normal modes normal single-chip mode normal expanded wide mode normal expanded narrow mode emulation expanded wide mode emulation expanded narrow mode special operating modes special single-chip mode with active background debug mode special test mode (motorola use only) special peripheral mode (motorola use only) each of the above modes of operation can be configured for three low power submodes device user guide ?9s12kt256dgv1/d v01.09 18 freescale semiconductor stop mode pseudo stop mode wait mode secure operation, preventing the unauthorized read and write of the memory contents. device user guide ?9s12kt256dgv1/d v01.09 19 freescale semiconductor 1.4 mc9s12kg(l)(c)128(64)(32) block diagram figure 1-1 mc9s12kg(l)(c)128(64)(32) block diagram 128k byte flash eeprom 8k byte ram reset extal xtal v dd1,2 v ss1,2 sci0 bkgd r/ w modb xirq noacc/ xclks system integration module (sim) vddr cpu12 periodic interrupt cop watchdog clock monitor single-wire bdm breakpoints pll vsspll xfc vddpll multiplexed address/data bus atd multiplexed wide bus multiplexed v ddx v ssx internal logic 2.5v narrow bus ppage v ddpll v sspll osc/pll 2.5v irq lstrb eclk moda pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 test addr12 addr11 addr10 addr9 addr8 addr15 addr14 addr13 data12 data11 data10 data9 data8 data15 data14 data13 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 addr4 addr3 addr2 addr1 addr0 addr7 addr6 addr5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 pe3 pe4 pe5 pe6 pe7 pe0 pe1 pe2 an02 an06 an00 an07 an01 an03 an04 an05 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 pt3 pt4 pt5 pt6 pt7 pt0 pt1 pt2 vrh vrl vdda vssa vrh vrl an10 an14 an08 an15 an09 an11 an12 an13 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa rxd txd miso mosi ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd txd pwm2 pwm6 pwm0 pwm7 pwm1 pwm3 pwm4 pwm5 pp3 pp4 pp5 pp6 pp7 pp0 pp1 pp2 pix2 pix0 pix1 pix3 ecs pk3 pk7 pk0 pk1 xaddr17 ecs xaddr14 xaddr15 xaddr16 sck ss ps6 ps7 spi0 iic sda scl pj6 pj7 can0 rxcan txcan pm1 pm0 pm2 pm3 pm4 pm5 pm6 pm7 kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ph2 kwj0 kwj1 pj0 pj1 i/o driver 3.3v/5v v dda v ssa a/d converter 3.3v/5v ddra ddrb pta ptb ddre pte pad pad ptk ddrk ptt ddrt ptp ddrp pts ddrs ptm ddrm pth ddrh ptj ddrj pk2 crg voltage regulator vssr vdd1,2 vss1,2 vregen v ddr v ssr voltage regulator 3.3v/5v pix4 pix5 pk4 pk5 xaddr18 xaddr19 voltage reference kwp2 kwp6 kwp0 kwp7 kwp1 kwp3 kwp4 kwp5 kwj6 kwj7 tim signals shown in bold are not available on n the 80 pin package module to port routing 2k byte eeprom pwm miso mosi sck ss spi1 miso mosi sck ss spi2 can4 rxcan txcan osc debugger device user guide ?9s12kt256dgv1/d v01.09 20 freescale semiconductor 1.5 mc9s12kt(g)256 block diagram figure 1-2 mc9s12kt(g)256 block diagram 256k byte flash eeprom 12k byte ram reset extal xtal v dd1,2 v ss1,2 sci0 bkgd r/ w modb xirq noacc/ xclks system integration module (sim) vddr cpu12 periodic interrupt cop watchdog clock monitor single-wire bdm breakpoints pll vsspll xfc vddpll multiplexed address/data bus atd0 multiplexed wide bus multiplexed v ddx v ssx internal logic 2.5v narrow bus ppage v ddpll v sspll osc/pll 2.5v irq lstrb eclk moda pa4 pa3 pa2 pa1 pa0 pa7 pa6 pa5 test addr12 addr11 addr10 addr9 addr8 addr15 addr14 addr13 data12 data11 data10 data9 data8 data15 data14 data13 pb4 pb3 pb2 pb1 pb0 pb7 pb6 pb5 addr4 addr3 addr2 addr1 addr0 addr7 addr6 addr5 data4 data3 data2 data1 data0 data7 data6 data5 data4 data3 data2 data1 data0 data7 data6 data5 pe3 pe4 pe5 pe6 pe7 pe0 pe1 pe2 an2 an6 an0 an7 an1 an3 an4 an5 pad03 pad04 pad05 pad06 pad07 pad00 pad01 pad02 ioc2 ioc6 ioc0 ioc7 ioc1 ioc3 ioc4 ioc5 pt3 pt4 pt5 pt6 pt7 pt0 pt1 pt2 vrh vrl vdda vssa vrh vrl an2 an6 an0 an7 an1 an3 an4 an5 pad11 pad12 pad13 pad14 pad15 pad08 pad09 pad10 vdda vssa rxd txd miso mosi ps3 ps4 ps5 ps0 ps1 ps2 sci1 rxd txd pwm2 pwm6 pwm0 pwm7 pwm1 pwm3 pwm4 pwm5 pp3 pp4 pp5 pp6 pp7 pp0 pp1 pp2 pix2 pix0 pix1 pix3 ecs pk3 pk7 pk0 pk1 xaddr17 ecs xaddr14 xaddr15 xaddr16 sck ss ps6 ps7 spi0 iic sda scl pj6 pj7 can0 rxcan txcan pm1 pm0 pm2 pm3 pm4 pm5 pm6 pm7 kwh2 kwh6 kwh0 kwh7 kwh1 kwh3 kwh4 kwh5 ph3 ph4 ph5 ph6 ph7 ph0 ph1 ph2 kwj0 kwj1 pj0 pj1 i/o driver 3.3v/5v v dda v ssa a/d converter 3.3v/5v ddra ddrb pta ptb ddre pte ad1 ad0 ptk ddrk ptt ddrt ptp ddrp pts ddrs ptm ddrm pth ddrh ptj ddrj pk2 crg voltage regulator vssr vdd1,2 vss1,2 vregen v ddr v ssr voltage regulator 3.3v/5v pix4 pix5 pk4 pk5 xaddr18 xaddr19 voltage reference kwp2 kwp6 kwp0 kwp7 kwp1 kwp3 kwp4 kwp5 kwj6 kwj7 tim signals shown in bold are not available on n the 80 pin package module to port routing 4k byte eeprom pwm miso mosi sck ss spi1 miso mosi sck ss spi2 can4 rxcan txcan osc debugger can1 rxcan txcan atd1 vrh vrl vdda vssa vrh vrl vdda vssa device user guide ?9s12kt256dgv1/d v01.09 21 freescale semiconductor 1.6 device memory map table 1-1 shows the device register map of the MC9S12KT256 and mc9s12kg256 after reset. table 1-2 shows the device register map of the mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64) after reset. table 1-1 mc9s12kt(g)256 device memory map address module size $000 - $017 core (ports a, b, e, modes, inits, test) 24 $018 reserved 1 $019 voltage regulator (vreg) 1 $01a - $01b device id register (partid) 2 $01c - $01f core (memsiz, irq, hprio) 4 $020 - $02f core (dbg) 16 $030 - $033 core (ppage, port k) 4 $034 - $03f clock and reset generator (pll, rti, cop) 12 $040 - $06f standard timer 16-bit 8 channels (tim) 48 $070 - $07f reserved 16 $080 - $09f analog to digital converter 10-bit 8 channels (atd0) 32 $0a0 - $0c7 reserved 40 $0c8 - $0cf serial communications interface 0 (sci0) 8 $0d0 - $0d7 serial communications interface 1 (sci1) 8 $0d8 - $0df serial peripheral interface 0 (spi0) 8 $0e0 - $0e7 inter integrated circuit bus (iic) 8 $0e8 - $0ef reserved 8 $0f0 - $0f7 serial peripheral interface 1 (spi1) 8 $0f8 - $0ff serial peripheral interface 2 (spi2) 8 $100- $10f flash control register 16 $110- $11b eeprom control register 12 $11c - $11f reserved 4 $120 - $13f analog to digital converter 10-bit 8 channels (atd1) 32 $140 - $17f motorola scalable controller area network 0 (can0) 64 $180 - $1bf motorola scalable controller area network 1 (can1) 64 $1c0 - $23f reserved 128 $240 - $27f port integration module (pim) 64 $280 - $2bf motorola scalable controller area network 4 (can4) 64 $2c0 - $2e7 pulse width modulator 8-bit 8 channels (pwm) 40 $2e8 - $3ff reserved 280 device user guide ?9s12kt256dgv1/d v01.09 22 freescale semiconductor table 1-2 mc9s12kg(l)(c)128(64)(32) device memory map address module size $000 - $017 core (ports a, b, e, modes, inits, test) 24 $018 reserved 1 $019 voltage regulator (vreg) 1 $01a - $01b device id register (partid) 2 $01c - $01f core (memsiz, irq, hprio) 4 $020 - $02f core (dbg) 16 $030 - $033 core (ppage, port k) 4 $034 - $03f clock and reset generator (pll, rti, cop) 12 $040 - $06f standard timer 16-bit 8 channels (tim) 48 $070 - $07f reserved 16 $080 - $0af analog to digital converter 10-bit 16 channels (atd) 48 $0b0 - $0c7 reserved 24 $0c8 - $0cf serial communications interface 0 (sci0) 8 $0d0 - $0d7 serial communications interface 1 (sci1) 8 $0d8 - $0df serial peripheral interface 0 (spi0) 8 $0e0 - $0e7 inter integrated circuit bus (iic) 8 $0e8 - $0ef reserved 8 $0f0 - $0f7 serial peripheral interface 1 (spi1) 8 $0f8 - $0ff serial peripheral interface 2 (spi2) 8 $100- $10f flash control register 16 $110- $11b eeprom control register 12 $11c - $13f reserved 36 $140 - $17f motorola scalable controller area network 0 (can0) 64 $180 - $23f reserved 192 $240 - $27f port integration module (pim) 64 $280 - $2bf motorola scalable controller area network 4 (can4) 64 $2c0 - $2e7 pulse width modulator 8-bit 8 channels (pwm) 40 $2e8 - $3ff reserved 280 device user guide ?9s12kt256dgv1/d v01.09 23 freescale semiconductor figure 1-4 illustrates the full user configurable device memory map of MC9S12KT256 and mc9s12kg256. figure 1-3 MC9S12KT256 and mc9s12kg256 memory map the ?ure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $1000 - $3fff: 12k ram $0000 - $0fff: 4k eeprom (1k hidden behind register space) $0000 $ffff $c000 $8000 $4000 $0400 $1000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window sixteen * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $1000 $3fff 12k bytes ram mappable to any 16k boundary $0000 $0fff 4k bytes eeprom mappable to any 4k boundary $0000 $03ff 1k register space mappable to any 2k boundary and alignable to top or bottom device user guide ?9s12kt256dgv1/d v01.09 24 freescale semiconductor figure 1-4 illustrates the full user configurable device memory map of mc9s12kg128, mc9s12kl128 and mc9s12kc128. figure 1-4 mc9s12kg128, mc9s12kl128 and mc9s12kc128 memory map the ?ure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $1fff: 8k ram (1k ram hidden behind register space) $0000 - $07ff: 2k eeprom (not visible) $0000 $ffff $c000 $8000 $4000 $0400 $0800 $1000 $2000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window eight * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $2000 $3fff 8k bytes ram mappable to any 8k boundary $0800 $0fff 2k bytes eeprom mappable to any 2k boundary $0000 $03ff 1k register space mappable to any 2k boundary device user guide ?9s12kt256dgv1/d v01.09 25 freescale semiconductor figure 1-5 illustrates the full user configurable device memory map of mc9s12kg64, mc9s12kl64 and mc9s12kc64. figure 1-5 mc9s12kg64, mc9s12kl64 and mc9s12kc64 memory map the ?ure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $0fff: 4k ram (1k ram hidden behind register space) $0000 - $03ff: 1k eeprom (not visible) $0000 $ffff $c000 $8000 $4000 $0400 $0800 $1000 $3000 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $c000 $ffff 16k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $bfff 16k page window four * 16k flash eeprom pages $4000 $7fff 16k fixed flash eeprom 0.5k, 1k, 2k or 4k protected sector $3000 $3fff 4k bytes ram mappable to any 4k boundary $0800 $0fff 1k bytes eeprom mappable to any 2k boundary $0000 $03ff 1k register space mappable to any 2k boundary (1k mapped two times in 2k space) device user guide ?9s12kt256dgv1/d v01.09 26 freescale semiconductor figure 1-6 illustrates the full user configurable device memory map of mc9s12kg32. figure 1-6 mc9s12kg32 memory map the ?ure shows a useful map, which is not the map out of reset. after reset the map is: $0000 - $03ff: register space $0000 - $07ff: 2k ram (1k ram hidden behind register space) $0000 - $03ff: 1k eeprom (not visible) $0000 $ffff $8000 $4000 $0400 $0800 $1000 $3800 $ff00 ext normal single chip expanded special single chip vectors vectors vectors $ff00 $ffff bdm (if active) $ffff 32k fixed flash eeprom 2k, 4k, 8k or 16k protected boot sector $8000 $3800 $3fff 2k bytes ram mappable to any 2k boundary $0800 $0fff 1k bytes eeprom mappable to any 2k boundary $0000 $03ff 1k register space mappable to any 2k boundary (1k mapped two times in 2k space) device user guide ?9s12kt256dgv1/d v01.09 27 freescale semiconductor 1.7 detailed register map the following tables show the detailed register map of the mc9s12k-family. $0000 - $000f mebi map 1 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 porta read: bit 7 6 5 4 3 2 1 bit 0 write: $0001 portb read: bit 7 6 5 4 3 2 1 bit 0 write: $0002 ddra read: bit 7 6 5 4 3 2 1 bit 0 write: $0003 ddrb read: bit 7 6 5 4 3 2 1 bit 0 write: $0004 reserved read: 0 0 0 0 0 0 0 0 write: $0005 reserved read: 0 0 0 0 0 0 0 0 write: $0006 reserved read: 0 0 0 0 0 0 0 0 write: $0007 reserved read: 0 0 0 0 0 0 0 0 write: $0008 porte read: bit 7 6 5 4 3 2 bit 1 bit 0 write: $0009 ddre read: bit 7 6 5 4 3 bit 2 0 0 write: $000a pear read: noacce 0 pipoe neclk lstre rdwe 0 0 write: $000b mode read: modc modb moda 0 ivis 0 emk eme write: $000c pucr read: pupke 0 0 pupee 0 0 pupbe pupae write: $000d rdriv read: rdpk 0 0 rdpe 0 0 rdpb rdpa write: $000e ebictl read: 0 0 0 0 0 0 0 estr write: $000f reserved read: 0 0 0 0 0 0 0 0 write: $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 initrm read: ram15 ram14 ram13 ram12 ram11 0 0 ramhal write: $0011 initrg read: 0 reg14 reg13 reg12 reg11 0 0 0 write: device user guide ?9s12kt256dgv1/d v01.09 28 freescale semiconductor $0012 initee read: ee15 ee14 ee13 ee12 ee11 0 0 eeon write: $0013 misc read: 0 0 0 0 exstr1 exstr0 romhm romon write: $0014 reserved read: 0 0 0 0 0 0 0 0 write: $0015 - $0016 int map 1 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0015 itcr read: 0 0 0 wrint adr3 adr2 adr1 adr0 write: $0016 itest read: inte intc inta int8 int6 int4 int2 int0 write: $0017 - $0017 mmc map 2 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0017 reserved read: 0 0 0 0 0 0 0 0 write: $0018 - $0018 miscellaneous peripherals (device guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0018 reserved read: 0 0 0 0 0 0 0 0 write: $0019 - $0019 vreg3v3 (voltage regulator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0019 vregctrl read: 0 0 0 0 0 lvds lvie lvif write: $001a - $001b miscellaneous peripherals (device guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001a partidh read: id15 id14 id13 id12 id11 id10 id9 id8 write: $001b partidl read: id7 id6 id5 id4 id3 id2 id1 id0 write: $0010 - $0014 mmc map 1 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 29 freescale semiconductor $001c - $001d mmc map 3 of 4 (hcs12 module mapping control, device guide) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001c memsiz0 read: reg_sw0 0 eep_sw1 eep_sw0 0 ram_sw2 ram_sw1 ram_sw0 write: $001d memsiz1 read: rom_sw1 rom_sw0 0 0 0 0 pag_sw1 pag_sw0 write: $001e - $001e mebi map 2 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001e intcr read: irqe irqen 0 0 0 0 0 0 write: $001f - $001f int map 2 of 2 (hcs12 interrupt) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $001f hprio read: psel7 psel6 psel5 psel4 psel3 psel2 psel1 0 write: $0020 - $002f dbg (including bkp) map 1of 1 (hcs12 debug) addres s name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0020 dbgc1 read dbgen arm trgsel begin dbgbrk 0 capmod - write $0021 dbgsc read af bf cf 0 trg - write $0022 dbgtbh read bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 - write $0023 dbgtbl read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - write $0024 dbgcnt read tbf 0 cnt - write $0025 dbgccx read pagsel extcmp - write $0026 dbgcch read bit 15 14 13 12 11 10 9 bit 8 write $0027 dbgccl read bit 7 6 5 4 3 2 1 bit 0 - write $0028 dbgc2 read bkaben full bdm tagab bkcen tagc rwcen rwc bkpct0 write $0029 dbgc3 read bkambh bkambl bkbmbh bkbmbl rwaen rwa rwben rwb bkpct1 write $002a dbgcax read pagsel extcmp bkp0x write $002b dbgcah read bit 15 14 13 12 11 10 9 bit 8 bkp0h write device user guide ?9s12kt256dgv1/d v01.09 30 freescale semiconductor $002c dbgcal read bit 7 6 5 4 3 2 1 bit 0 bkp0l write $002d dbgcbx read pagsel extcmp bkp1x write $002e dbgcbh read bit 15 14 13 12 11 10 9 bit 8 bkp1h write $002f dbgcbl read bit 7 6 5 4 3 2 1 bit 0 bkp1l write $0030 - $0031 mmc map 4 of 4 (hcs12 module mapping control) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0030 ppage read: 0 0 pix5 pix4 pix3 pix2 pix1 pix0 write: $0031 reserved read: 0 0 0 0 0 0 0 0 write: $0032 - $0033 mebi map 3 of 3 (hcs12 multiplexed external bus interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0032 portk read: bit 7 6 5 4 3 2 1 bit 0 write: $0033 ddrk read: bit 7 6 5 4 3 2 1 bit 0 write: $0034 - $003f crg (clock and reset generator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0034 synr read: 0 0 syn5 syn4 syn3 syn2 syn1 syn0 write: $0035 refdv read: 0 0 0 0 refdv3 refdv2 refdv1 refdv0 write: $0036 ctflg test only read: tout7 tout6 tout5 tout4 tout3 tout2 tout1 tout0 write: $0037 crgflg read: rtif prof 0 lockif lock track scmif scm write: $0038 crgint read: rtie 0 0 lockie 0 0 scmie 0 write: $0039 clksel read: pllsel pstp syswai roawai pllwai cwai rtiwai copwai write: $003a pllctl read: cme pllon auto acq 0 pre pce scme write: $003b rtictl read: 0 rtr6 rtr5 rtr4 rtr3 rtr2 rtr1 rtr0 write: $003c copctl read: wcop rsbck 0 0 0 cr2 cr1 cr0 write: $0020 - $002f dbg (including bkp) map 1of 1 (hcs12 debug) addres s name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 31 freescale semiconductor $003d forbyp test only read: rtibyp copbyp 0 pllbyp 0 0 fcm 0 write: $003e ctctl test only read: tctl7 tctl6 tctl5 tctl4 tclt3 tctl2 tctl1 tctl0 write: $003f armcop read: 0 0 0 0 0 0 0 0 write: bit 7 6 5 4 3 2 1 bit 0 $0040 - $006f tim (timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0040 tios read: ios7 ios6 ios5 ios4 ios3 ios2 ios1 ios0 write: $0041 cforc read: 0 0 0 0 0 0 0 0 write: foc7 foc6 foc5 foc4 foc3 foc2 foc1 foc0 $0042 oc7m read: oc7m7 oc7m6 oc7m5 oc7m4 oc7m3 oc7m2 oc7m1 oc7m0 write: $0043 oc7d read: oc7d7 oc7d6 oc7d5 oc7d4 oc7d3 oc7d2 oc7d1 oc7d0 write: $0044 tcnt (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0045 tcnt (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0046 tscr1 read: ten tswai tsfrz tffca 0 0 0 0 write: $0047 ttov read: tov7 tov6 tov5 tov4 tov3 tov2 tov1 tov0 write: $0048 tctl1 read: om7 ol7 om6 ol6 om5 ol5 om4 ol4 write: $0049 tctl2 read: om3 ol3 om2 ol2 om1 ol1 om0 ol0 write: $004a tctl3 read: edg7b edg7a edg6b edg6a edg5b edg5a edg4b edg4a write: $004b tctl4 read: edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a write: $004c tie read: c7i c6i c5i c4i c3i c2i c1i c0i write: $004d tscr2 read: toi 0 0 0 tcre pr2 pr1 pr0 write: $004e tflg1 read: c7f c6f c5f c4f c3f c2f c1f c0f write: $004f tflg2 read: tof 0 0 0 0 0 0 0 write: $0050 tc0 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0051 tc0 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0052 tc1 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0053 tc1 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0034 - $003f crg (clock and reset generator) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 32 freescale semiconductor $0054 tc2 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0055 tc2 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0056 tc3 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0057 tc3 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0058 tc4 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $0059 tc4 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $005a tc5 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005b tc5 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $005c tc6 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005d tc6 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $005e tc7 (hi) read: bit 15 14 13 12 11 10 9 bit 8 write: $005f tc7 (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0060 pactl read: 0 paen pamod pedge clk1 clk0 paov i pa i write: $0061 paflg read: 0 0 0 0 0 0 paov f paif write: $0062 pacnt (hi) read: bit 7 6 5 4 3 2 1 bit 0 write: $0063 pacnt (lo) read: bit 7 6 5 4 3 2 1 bit 0 write: $0064 reserved read: 0 0 0 0 0 0 0 0 write: $0065 reserved read: 0 0 0 0 0 0 0 0 write: $0066 reserved read: 0 0 0 0 0 0 0 0 write: $0067 reserved read: 0 0 0 0 0 0 0 0 write: $0068 reserved read: 0 0 0 0 0 0 0 0 write: $0069 reserved read: 0 0 0 0 0 0 0 0 write: $006a reserved read: 0 0 0 0 0 0 0 0 write: $006b reserved read: 0 0 0 0 0 0 0 0 write: $006c reserved read: 0 0 0 0 0 0 0 0 write: $0040 - $006f tim (timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 33 freescale semiconductor $006d reserved read: 0 0 0 0 0 0 0 0 write: $006e reserved read: 0 0 0 0 0 0 0 0 write: $006f reserved read: 0 0 0 0 0 0 0 0 write: $0070 - $007f reserved space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0070 - $007f reserved read: 0 0 0 0 0 0 0 0 write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0080 atdctl0 read: 0 0 0 0 wrap3 wrap2 wrap1 wrap0 write: $0081 atdctl1 read: etrigsel 0 0 0 etrigch3 etrigch2 etrigch1 etrigch0 write: $0082 atdctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0083 atdctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0084 atdctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0085 atdctl5 read: djm dsgn scan mult 0 cc cb ca write: $0086 atdstat0 read: scf 0 etorf fifor 0 cc2 cc1 cc0 write: $0087 reserved read: 0 0 0 0 0 0 0 0 write: $0088 atdtest0 read: 0 0 0 0 0 0 0 0 write: $0089 atdtest1 read: 0 0 0 0 0 0 0 sc write: $008a atdstat0 read: ccf15 ccf14 ccf13 ccf12 ccf11 ccf10 ccf9 ccf8 write: $008b atdstat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $008c atddien1 read: ien15 ien14 ien13 ien12 ien11 ien10 ien9 ien8 write: $008d atddien0 read: ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 write: $008e portad1 read: ptad15 ptad14 ptad13 ptad12 ptad11 ptad10 ptad9 ptad8 write: $008f portad0 read: ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 write: $0040 - $006f tim (timer 16 bit 8 channels) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 34 freescale semiconductor $0090 atddr0h read: bit15 14 13 12 11 10 9 bit8 write: $0091 atddr0l read: bit7 bit6 0 0 0 0 0 0 write: $0092 atddr1h read: bit15 14 13 12 11 10 9 bit8 write: $0093 atddr1l read: bit7 bit6 0 0 0 0 0 0 write: $0094 atddr2h read: bit15 14 13 12 11 10 9 bit8 write: $0095 atddr2l read: bit7 bit6 0 0 0 0 0 0 write: $0096 atddr3h read: bit15 14 13 12 11 10 9 bit8 write: $0097 atddr3l read: bit7 bit6 0 0 0 0 0 0 write: $0098 atddr4h read: bit15 14 13 12 11 10 9 bit8 write: $0099 atddr4l read: bit7 bit6 0 0 0 0 0 0 write: $009a atddr5h read: bit15 14 13 12 11 10 9 bit8 write: $009b atddr5l read: bit7 bit6 0 0 0 0 0 0 write: $009c atddr6h read: bit15 14 13 12 11 10 9 bit8 write: $009d atddr6l read: bit7 bit6 0 0 0 0 0 0 write: $009e atddr7h read: bit15 14 13 12 11 10 9 bit8 write: $009f atddr7l read: bit7 bit6 0 0 0 0 0 0 write: $00a0 atddr8h read: bit15 14 13 12 11 10 9 bit8 write: $00a1 atddr8l read: bit7 bit6 0 0 0 0 0 0 write: $00a2 atddr9h read: bit15 14 13 12 11 10 9 bit8 write: $00a3 atddr9l read: bit7 bit6 0 0 0 0 0 0 write: $00a4 atddr10h read: bit15 14 13 12 11 10 9 bit8 write: $00a5 atddr10l read: bit7 bit6 0 0 0 0 0 0 write: $00a6 atddr11h read: bit15 14 13 12 11 10 9 bit8 write: $00a7 atddr11l read: bit7 bit6 0 0 0 0 0 0 write: $00a8 atddr12h read: bit15 14 13 12 11 10 9 bit8 write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 35 freescale semiconductor $00a9 atddr12l read: bit7 bit6 0 0 0 0 0 0 write: $00aa atddr13h read: bit15 14 13 12 11 10 9 bit8 write: $00ab atddr13l read: bit7 bit6 0 0 0 0 0 0 write: $00ac atddr14h read: bit15 14 13 12 11 10 9 bit8 write: $00ad atddr14l read: bit7 bit6 0 0 0 0 0 0 write: $00ae atddr15h read: bit15 14 13 12 11 10 9 bit8 write: $00af atddr15l read: bit7 bit6 0 0 0 0 0 0 write: notes : 1. registers only available on mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64) $00b0 - $00c7 reserved space 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00b0 - $00c7 reserved read: 0 0 0 0 0 0 0 0 write: notes : 1. reserved space for mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64) $0080 - $009f atd0 (analog to digital converter 10 bit 8 channel) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0080 atd0ctl0 read: 0 0 0 0 0 wrap2 wrap1 wrap0 write: $0081 atd0ctl1 read: etrigsel 0 0 0 0 etrigch2 etrigch1 etrigch0 write: $0082 atd0ctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0083 atd0ctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0084 atd0ctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0085 atd0ctl5 read: djm dsgn scan mult 0 cc cb ca write: $0086 atd0stat0 read: scf 0 etorf fifor 0 cc2 cc1 cc0 write: $0087 reserved read: 0 0 0 0 0 0 0 0 write: $0088 atd0test0 read: 0 0 0 0 0 0 0 0 write: $0089 atd0test1 read: 0 0 0 0 0 0 0 sc write: $0080 - $00af atd (analog to digital converter 10 bit 16 channel) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 36 freescale semiconductor $008a reserved read: 0 0 0 0 0 0 0 0 write: $008b atd0stat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $008c reserved read: 0 0 0 0 0 0 0 0 write: $008d atd0dien read: ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 write: $008e reserved read: 0 0 0 0 0 0 0 0 write: $008f portad0 read: ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 write: $0090 atd0dr0h read: bit15 14 13 12 11 10 9 bit8 write: $0091 atd0dr0l read: bit7 bit6 0 0 0 0 0 0 write: $0092 atd0dr1h read: bit15 14 13 12 11 10 9 bit8 write: $0093 atd0dr1l read: bit7 bit6 0 0 0 0 0 0 write: $0094 atd0dr2h read: bit15 14 13 12 11 10 9 bit8 write: $0095 atd0dr2l read: bit7 bit6 0 0 0 0 0 0 write: $0096 atd0dr3h read: bit15 14 13 12 11 10 9 bit8 write: $0097 atd0dr3l read: bit7 bit6 0 0 0 0 0 0 write: $0098 atd0dr4h read: bit15 14 13 12 11 10 9 bit8 write: $0099 atd0dr4l read: bit7 bit6 0 0 0 0 0 0 write: $009a atd0dr5h read: bit15 14 13 12 11 10 9 bit8 write: $009b atd0dr5l read: bit7 bit6 0 0 0 0 0 0 write: $009c atd0dr6h read: bit15 14 13 12 11 10 9 bit8 write: $009d atd0dr6l read: bit7 bit6 0 0 0 0 0 0 write: $009e atd0dr7h read: bit15 14 13 12 11 10 9 bit8 write: $009f atd0dr7l read: bit7 bit6 0 0 0 0 0 0 write: notes : 1. registers only available on MC9S12KT256 and mc9s12kg256 $0080 - $009f atd0 (analog to digital converter 10 bit 8 channel) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 37 freescale semiconductor $00a0 - $00c7 reserved space 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00a0 - $00c7 reserved read: 0 0 0 0 0 0 0 0 write: notes : 1. reserved space for MC9S12KT256 and mc9s12kg256 $00c8 - $00cf sci0 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00c8 sci0bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00c9 sci0bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00ca sci0cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00cb sci0cr2 read: tie tcie rie ilie te re rwu sbk write: $00cc sci0sr1 read: tdre tc rdrf idle or nf fe pf write: $00cd sci0sr2 read: 0 0 0 0 0 brk13 txdir raf write: $00ce sci0drh read: r8 t8 0 0 0 0 0 0 write: $00cf sci0drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 $00d0 - $00d7 sci1 (asynchronous serial interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d0 sci1bdh read: 0 0 0 sbr12 sbr11 sbr10 sbr9 sbr8 write: $00d1 sci1bdl read: sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 write: $00d2 sci1cr1 read: loops sciswai rsrc m wake ilt pe pt write: $00d3 sci1cr2 read: tie tcie rie ilie te re rwu sbk write: $00d4 sci1sr1 read: tdre tc rdrf idle or nf fe pf write: $00d5 sci1sr2 read: 0 0 0 0 0 brk13 txdir raf write: $00d6 sci1drh read: r8 t8 0 0 0 0 0 0 write: $00d7 sci1drl read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 device user guide ?9s12kt256dgv1/d v01.09 38 freescale semiconductor $00d8 - $00df spi0 (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00d8 spi0cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00d9 spi0cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00da spi0br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00db spi0sr read: spif 0 sptef modf 0 0 0 0 write: $00dc reserved read: 0 0 0 0 0 0 0 0 write: $00dd spi0dr read: bit7 6 5 4 3 2 1 bit0 write: $00de reserved read: 0 0 0 0 0 0 0 0 write: $00df reserved read: 0 0 0 0 0 0 0 0 write: $00e0 - $00e7 iic (inter ic bus) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e0 ibad read: adr7 adr6 adr5 adr4 adr3 adr2 adr1 0 write: $00e1 ibfd read: ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 write: $00e2 ibcr read: iben ibie ms/ sl tx/ rx txak 0 0 ibswai write: rsta $00e3 ibsr read: tcf iaas ibb ibal 0 srw ibif rxak write: $00e4 ibdr read: d7 d6 d5 d4 d3 d2 d1 d 0 write: $00e5 reserved read: 0 0 0 0 0 0 0 0 write: $00e6 reserved read: 0 0 0 0 0 0 0 0 write: $00e7 reserved read: 0 0 0 0 0 0 0 0 write: $00e8 - $00ef reserved space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00e8 - $00ef reserved read: 0 0 0 0 0 0 0 0 write: device user guide ?9s12kt256dgv1/d v01.09 39 freescale semiconductor $00f0 - $00f7 spi1 (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00f0 spi1cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00f1 spi1cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00f2 spi1br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00f3 spi1sr read: spif 0 sptef modf 0 0 0 0 write: $00f4 reserved read: 0 0 0 0 0 0 0 0 write: $00f5 spi1dr read: bit7 6 5 4 3 2 1 bit0 write: $00f6 reserved read: 0 0 0 0 0 0 0 0 write: $00f7 reserved read: 0 0 0 0 0 0 0 0 write: $00f8 - $00ff spi2 (serial peripheral interface) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $00f8 spi2cr1 read: spie spe sptie mstr cpol cpha ssoe lsbfe write: $00f9 spi2cr2 read: 0 0 0 modfen bidiroe 0 spiswai spc0 write: $00fa spi2br read: 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 write: $00fb spi2sr read: spif 0 sptef modf 0 0 0 0 write: $00fc reserved read: 0 0 0 0 0 0 0 0 write: $00fd spi2dr read: bit7 6 5 4 3 2 1 bit0 write: $00fe reserved read: 0 0 0 0 0 0 0 0 write: $00ff reserved read: 0 0 0 0 0 0 0 0 write: $0100 - $010f flash control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0100 fclkdiv read: fdivld prdiv8 fdiv5 fdiv4 fdiv3 fdiv2 fdiv1 fdiv0 write: $0101 fsec read: keyen rnv5 rnv4 rnv3 rnv2 sec write: $0102 ftstmod read: 0 0 0 wrall 1 fdfd 0 0 0 write: $0103 fcnfg read: cbeie ccie keyacc 0 dfdie 0 0 bksel (1) write: device user guide ?9s12kt256dgv1/d v01.09 40 freescale semiconductor $0104 fprot read: fpopen rnv6 fphdis fphs fpldis fpls write: $0105 fstat read: cbeif ccif pviol accerr dfdif blank 0 0 write: $0106 fcmd read: 0 cmdb write: $0107 fctl 2 read: nv7 nv6 nv5 nv4 nv3 nv2 nv1 nv0 write: $0108 faddrhi read: faddrhi write: $0109 faddrlo read: faddrlo write: $010a fdatahi read: fdatahi write: $010b fdatalo read: fdatalo write: $010c reserved read: 0 0 0 0 0 0 0 0 write: $010d reserved read: 0 0 0 0 0 0 0 0 write: $010e reserved read: 0 0 0 0 0 0 0 0 write: $010f reserved read: 0 0 0 0 0 0 0 0 write: notes : 1. bit only available on MC9S12KT256 and mc9s12kg256. 2. register only available on MC9S12KT256 and mc9s12kg256. $0110 - $011b eeprom control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0110 eclkdiv read: edivld prdiv8 ediv5 ediv4 ediv3 ediv2 ediv1 ediv0 write: $0111 reserved read: 0 0 0 0 0 0 0 0 write: $0112 reserved for factory test read: 0 0 0 0 0 0 0 0 write: $0113 ecnfg read: cbeie ccie 0 0 0 0 0 0 write: $0114 eprot read: epopen nv6 nv5 nv4 epdis ep2 ep1 ep0 write: $0115 estat read: cbeif ccif pviol accerr 0 blank 0 0 write: $0116 ecmd read: 0 cmdb6 cmdb5 0 0 cmdb2 0 cmdb0 write: $0117 reserved for factory test read: 0 0 0 0 0 0 0 0 write: $0118 eaddrhi read: 0 0 0 0 0 10 9 bit 8 write: $0100 - $010f flash control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 41 freescale semiconductor $0119 eaddrlo read: bit 7 6 5 4 3 2 1 bit 0 write: $011a edatahi read: bit 15 14 13 12 11 10 9 bit 8 write: $011b edatalo read: bit 7 6 5 4 3 2 1 bit 0 write: $011c - $011f reserved space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $011c - $011f reserved read: 0 0 0 0 0 0 0 0 write: $0120 - $013f atd1 (analog to digital converter 10 bit 8 channel) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0120 atd1ctl0 read: 0 0 0 0 0 wrap2 wrap1 wrap0 write: $0121 atd1ctl1 read: etrigsel 0 0 0 0 etrigch2 etrigch1 etrigch0 write: $0122 atd1ctl2 read: adpu affc awai etrigle etrigp etrig ascie ascif write: $0123 atd1ctl3 read: 0 s8c s4c s2c s1c fifo frz1 frz0 write: $0124 atd1ctl4 read: sres8 smp1 smp0 prs4 prs3 prs2 prs1 prs0 write: $0125 atd1ctl5 read: djm dsgn scan mult 0 cc cb ca write: $0126 atd1stat0 read: scf 0 etorf fifor 0 cc2 cc1 cc0 write: $0127 reserved read: 0 0 0 0 0 0 0 0 write: $0128 atd1test0 read: 0 0 0 0 0 0 0 0 write: $0129 atd1test1 read: 0 0 0 0 0 0 0 sc write: $012a reserved read: 0 0 0 0 0 0 0 0 write: $012b atd1stat1 read: ccf7 ccf6 ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 write: $012c reserved read: 0 0 0 0 0 0 0 0 write: $012d atd1dien read: ien7 ien6 ien5 ien4 ien3 ien2 ien1 ien0 write: $012e reserved read: 0 0 0 0 0 0 0 0 write: $012f portad1 read: ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 write: $0110 - $011b eeprom control register address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 42 freescale semiconductor $0130 atd1dr0h read: bit15 14 13 12 11 10 9 bit8 write: $0131 atd1dr0l read: bit7 bit6 0 0 0 0 0 0 write: $0132 atd1dr1h read: bit15 14 13 12 11 10 9 bit8 write: $0133 atd1dr1l read: bit7 bit6 0 0 0 0 0 0 write: $0134 atd1dr2h read: bit15 14 13 12 11 10 9 bit8 write: $0135 atd1dr2l read: bit7 bit6 0 0 0 0 0 0 write: $0136 atd1dr3h read: bit15 14 13 12 11 10 9 bit8 write: $0137 atd1dr3l read: bit7 bit6 0 0 0 0 0 0 write: $0138 atd1dr4h read: bit15 14 13 12 11 10 9 bit8 write: $0139 atd1dr4l read: bit7 bit6 0 0 0 0 0 0 write: $013a atd1dr5h read: bit15 14 13 12 11 10 9 bit8 write: $013b atd1dr5l read: bit7 bit6 0 0 0 0 0 0 write: $013c atd1dr6h read: bit15 14 13 12 11 10 9 bit8 write: $013d atd1dr6l read: bit7 bit6 0 0 0 0 0 0 write: $013e atd1dr7h read: bit15 14 13 12 11 10 9 bit8 write: $013f atd1dr7l read: bit7 bit6 0 0 0 0 0 0 write: notes : 1. registers only available on MC9S12KT256 and mc9s12kg256. reserved space for mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64). $0140 - $017f can0 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0140 can0ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0141 can0ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0142 can0btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0143 can0btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0144 can0rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0120 - $013f atd1 (analog to digital converter 10 bit 8 channel) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 43 freescale semiconductor $0145 can0rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0146 can0tflg read: 0 0 0 0 0 txe2 txe1 txe0 write: $0147 can0tier read: 0 0 0 0 0 txeie2 txeie1 txeie0 write: $0148 can0tarq read: 0 0 0 0 0 abtrq2 abtrq1 abtrq0 write: $0149 can0taak read: 0 0 0 0 0 abtak2 abtak1 abtak0 write: $014a can0tbsel read: 0 0 0 0 0 tx2 tx1 tx0 write: $014b can0idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $014c reserved read: 0 0 0 0 0 0 0 0 write: $014d reserved read: 0 0 0 0 0 0 0 0 write: $014e can0rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $014f can0txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0150 - $0153 can0idar0 - can0idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0154 - $0157 can0idmr0 - can0idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0158 - $015b can0idar4 - can0idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $015c - $015f can0idmr4 - can0idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0160 - $016f can0rxfg read: foreground receive buffer see (table 1-3) write: $0170 - $017f can0txfg read: foreground transmit buffer see (table 1-3) write: table 1-3 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $xxx0 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 standard id read: id10 id9 id8 id7 id6 id5 id4 id3 canxridr0 write: $xxx1 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 standard id read: id2 id1 id0 rtr ide=0 canxridr1 write: $xxx2 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 standard id read: canxridr2 write: $xxx3 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr standard id read: canxridr3 write: $0140 - $017f can0 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 44 freescale semiconductor $xxx4- $xxxb canxrdsr0 - canxrdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $xxxc canrxdlr read: dlc3 dlc2 dlc1 dlc0 write: $xxxd reserved read: write: $xxxe canxrtsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xxxf canxrtsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $xx10 extended id read: id28 id27 id26 id25 id24 id23 id22 id21 canxtidr0 write: standard id read: id10 id9 id8 id7 id6 id5 id4 id3 write: $xx10 extended id read: id20 id19 id18 srr=1 ide=1 id17 id16 id15 canxtidr1 write: standard id read: id2 id1 id0 rtr ide=0 write: $xx12 extended id read: id14 id13 id12 id11 id10 id9 id8 id7 canxtidr2 write: standard id read: write: $xx13 extended id read: id6 id5 id4 id3 id2 id1 id0 rtr canxtidr3 write: standard id read: write: $xx14- $xx1b canxtdsr0 - canxtdsr7 read: db7 db6 db5 db4 db3 db2 db1 db0 write: $xx1c canxtdlr read: dlc3 dlc2 dlc1 dlc0 write: $xx1d conxttbpr read: prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 write: $xx1e canxttsrh read: tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 write: $xx1f canxttsrl read: tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 write: $0180 - $01bf can1 (motorola scalable can - mscan) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0180 can1ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0181 can1ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0182 can1btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0183 can1btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: table 1-3 detailed mscan foreground receive and transmit buffer layout address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 45 freescale semiconductor $0184 can1rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0185 can1rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0186 can1tflg read: 0 0 0 0 0 txe2 txe1 txe0 write: $0187 can1tier read: 0 0 0 0 0 txeie2 txeie1 txeie0 write: $0188 can1tarq read: 0 0 0 0 0 abtrq2 abtrq1 abtrq0 write: $0189 can1taak read: 0 0 0 0 0 abtak2 abtak1 abtak0 write: $018a can1tbsel read: 0 0 0 0 0 tx2 tx1 tx0 write: $018b can1idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $018c reserved read: 0 0 0 0 0 0 0 0 write: $018d reserved read: 0 0 0 0 0 0 0 0 write: $018e can1rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $018f can1txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0190 can1idar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0191 can1idar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0192 can1idar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0193 can1idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0194 can1idmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0195 can1idmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0196 can1idmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0197 can1idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0198 can1idar4 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0199 can1idar5 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019a can1idar6 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019b can1idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $019c can1idmr4 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0180 - $01bf can1 (motorola scalable can - mscan) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 46 freescale semiconductor $019d can1idmr5 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $019e can1idmr6 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $019f can1idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $01a0 - $01af can1rxfg read: foreground receive buffer see (table 1-3) write: $01b0 - $01bf can1txfg read: foreground transmit buffer see (table 1-3) write: notes : 1. registers only available on MC9S12KT256. reserved space for mc9s12kg256(128)(64)(32), mc9s12kl128(64) and mc9s12kc128(64). $01c0 - $023f reserved space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $01c0 - $023f reserved read: 0 0 0 0 0 0 0 0 write: $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0240 ptt read: ptt7 ptt6 ptt5 ptt4 ptt3 ptt2 ptt1 ptt0 write: $0241 ptit read: ptit7 ptit6 ptit5 ptit4 ptit3 ptit2 ptit1 ptit0 write: $0242 ddrt read: ddrt7 ddrt7 ddrt5 ddrt4 ddrt3 ddrt2 ddrt1 ddrt0 write: $0243 rdrt read: rdrt7 rdrt6 rdrt5 rdrt4 rdrt3 rdrt2 rdrt1 rdrt0 write: $0244 pert read: pert7 pert6 pert5 pert4 pert3 pert2 pert1 pert0 write: $0245 ppst read: ppst7 ppst6 ppst5 ppst4 ppst3 ppst2 ppst1 ppst0 write: $0246 reserved read: 0 0 0 0 0 0 0 0 write: $0247 reserved read: 0 0 0 0 0 0 0 0 write: $0248 pts read: pts7 pts6 pts5 pts4 pts3 pts2 pts1 pts0 write: $0249 ptis read: ptis7 ptis6 ptis5 ptis4 ptis3 ptis2 ptis1 ptis0 write: $024a ddrs read: ddrs7 ddrs7 ddrs5 ddrs4 ddrs3 ddrs2 ddrs1 ddrs0 write: $024b rdrs read: rdrs7 rdrs6 rdrs5 rdrs4 rdrs3 rdrs2 rdrs1 rdrs0 write: $0180 - $01bf can1 (motorola scalable can - mscan) 1 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 47 freescale semiconductor $024c pers read: pers7 pers6 pers5 pers4 pers3 pers2 pers1 pers0 write: $024d ppss read: ppss7 ppss6 ppss5 ppss4 ppss3 ppss2 ppss1 ppss0 write: $024e woms read: woms7 woms6 woms5 woms4 woms3 woms2 woms1 woms0 write: $024f reserved read: 0 0 0 0 0 0 0 0 write: $0250 ptm read: ptm7 ptm6 ptm5 ptm4 ptm3 ptm2 ptm1 ptm0 write: $0251 ptim read: ptim7 ptim6 ptim5 ptim4 ptim3 ptim2 ptim1 ptim0 write: $0252 ddrm read: ddrm7 ddrm7 ddrm5 ddrm4 ddrm3 ddrm2 ddrm1 ddrm0 write: $0253 rdrm read: rdrm7 rdrm6 rdrm5 rdrm4 rdrm3 rdrm2 rdrm1 rdrm0 write: $0254 perm read: perm7 perm6 perm5 perm4 perm3 perm2 perm1 perm0 write: $0255 ppsm read: ppsm7 ppsm6 ppsm5 ppsm4 ppsm3 ppsm2 ppsm1 ppsm0 write: $0256 womm read: womm7 womm6 womm5 womm4 womm3 womm2 womm1 womm0 write: $0257 modrr read: 0 modrr6 modrr5 modrr4 modrr3 modrr2 modrr1 modrr0 write: $0258 ptp read: ptp7 ptp6 ptp5 ptp4 ptp3 ptp2 ptp1 ptp0 write: $0259 ptip read: ptip7 ptip6 ptip5 ptip4 ptip3 ptip2 ptip1 ptip0 write: $025a ddrp read: ddrp7 ddrp7 ddrp5 ddrp4 ddrp3 ddrp2 ddrp1 ddrp0 write: $025b rdrp read: rdrp7 rdrp6 rdrp5 rdrp4 rdrp3 rdrp2 rdrp1 rdrp0 write: $025c perp read: perp7 perp6 perp5 perp4 perp3 perp2 perp1 perp0 write: $025d ppsp read: ppsp7 ppsp6 ppsp5 ppsp4 ppsp3 ppsp2 ppsp1 ppss0 write: $025e piep read: piep7 piep6 piep5 piep4 piep3 piep2 piep1 piep0 write: $025f pifp read: pifp7 pifp6 pifp5 pifp4 pifp3 pifp2 pifp1 pifp0 write: $0260 pth read: pth7 pth6 pth5 pth4 pth3 pth2 pth1 pth0 write: $0261 ptih read: ptih7 ptih6 ptih5 ptih4 ptih3 ptih2 ptih1 ptih0 write: $0262 ddrh read: ddrh7 ddrh7 ddrh5 ddrh4 ddrh3 ddrh2 ddrh1 ddrh0 write: $0263 rdrh read: rdrh7 rdrh6 rdrh5 rdrh4 rdrh3 rdrh2 rdrh1 rdrh0 write: $0264 perh read: perh7 perh6 perh5 perh4 perh3 perh2 perh1 perh0 write: $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 48 freescale semiconductor $0265 ppsh read: ppsh7 ppsh6 ppsh5 ppsh4 ppsh3 ppsh2 ppsh1 ppsh0 write: $0266 pieh read: pieh7 pieh6 pieh5 pieh4 pieh3 pieh2 pieh1 pieh0 write: $0267 pifh read: pifh7 pifh6 pifh5 pifh4 pifh3 pifh2 pifh1 pifh0 write: $0268 ptj read: ptj7 ptj6 0 0 0 0 ptj1 ptj0 write: $0269 ptij read: ptij7 ptij6 0 0 0 0 ptij1 ptij0 write: $026a ddrj read: ddrj7 ddrj7 0 0 0 0 ddrj1 ddrj0 write: $026b rdrj read: rdrj7 rdrj6 0 0 0 0 rdrj1 rdrj0 write: $026c perj read: perj7 perj6 0 0 0 0 perj1 perj0 write: $026d ppsj read: ppsj7 ppsj6 0 0 0 0 ppsj1 ppsj0 write: $026e piej read: piej7 piej6 0 0 0 0 piej1 piej0 write: $026f pifj read: pifj7 pifj6 0 0 0 0 pifj1 pifj0 write: $0270 - $027f reserved read: $0280 - $02bf can4 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0280 can4ctl0 read: rxfrm rxact cswai synch time wupe slprq initrq write: $0281 can4ctl1 read: cane clksrc loopb listen 0 wupm slpak initak write: $0282 can4btr0 read: sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 write: $0283 can4btr1 read: samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 write: $0284 can4rflg read: wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf write: $0285 can4rier read: wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie write: $0286 can4tflg read: 0 0 0 0 0 txe2 txe1 txe0 write: $0287 can4tier read: 0 0 0 0 0 txeie2 txeie1 txeie0 write: $0288 can4tarq read: 0 0 0 0 0 abtrq2 abtrq1 abtrq0 write: $0289 can4taak read: 0 0 0 0 0 abtak2 abtak1 abtak0 write: $028a can4tbsel read: 0 0 0 0 0 tx2 tx1 tx0 write: $0240 - $027f pim (port integration module) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 49 freescale semiconductor $028b can4idac read: 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 write: $028c reserved read: 0 0 0 0 0 0 0 0 write: $028d reserved read: 0 0 0 0 0 0 0 0 write: $028e can4rxerr read: rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 write: $028f can4txerr read: txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 write: $0290 can4idar0 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0291 can4idar1 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0292 can4idar2 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0293 can4idar3 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0294 can4idmr0 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0295 can4idmr1 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0296 can4idmr2 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0297 can4idmr3 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $0298 can4idar4 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $0299 can4idar5 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $029a can4idar6 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $029b can4idar7 read: ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 write: $029c can4idmr4 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $029d can4idmr5 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $029e can4idmr6 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $029f can4idmr7 read: am7 am6 am5 am4 am3 am2 am1 am0 write: $02a0 - $02af can4rxfg read: foreground receive buffer see (table 1-3) write: $02b0 - $02bf can4txfg read: foreground transmit buffer see (table 1-3) write: $0280 - $02bf can4 (motorola scalable can - mscan) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 50 freescale semiconductor $02c0 - $02e7 pwm (pulse width modulator 8 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02c0 pwme read: pwme7 pwme6 pwme5 pwme4 pwme3 pwme2 pwme1 pwme0 write: $02c1 pwmpol read: ppol7 ppol6 ppol5 ppol4 ppol3 ppol2 ppol1 ppol0 write: $02c2 pwmclk read: pclk7 pclk6 pclk5 pclk4 pclk3 pclk2 pclk1 pclk0 write: $02c3 pwmprclk read: 0 pckb2 pckb1 pckb0 0 pcka2 pcka1 pcka0 write: $02c4 pwmcae read: cae7 cae6 cae5 cae4 cae3 cae2 cae1 cae0 write: $02c5 pwmctl read: con67 con45 con23 con01 pswai pfrz 0 0 write: $02c6 pwmtst test only read: 0 0 0 0 0 0 0 0 write: $02c7 pwmprsc read: 0 0 0 0 0 0 0 0 write: $02c8 pwmscla read: bit 7 6 5 4 3 2 1 bit 0 write: $02c9 pwmsclb read: bit 7 6 5 4 3 2 1 bit 0 write: $02ca pwmscnta read: 0 0 0 0 0 0 0 0 write: $02cb pwmscntb read: 0 0 0 0 0 0 0 0 write: $02cc pwmcnt0 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02cd pwmcnt1 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02ce pwmcnt2 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02cf pwmcnt3 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02d0 pwmcnt4 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02d1 pwmcnt5 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02d2 pwmcnt6 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02d3 pwmcnt7 read: bit 7 6 5 4 3 2 1 bit 0 write: 0 0 0 0 0 0 0 0 $02d4 pwmper0 read: bit 7 6 5 4 3 2 1 bit 0 write: $02d5 pwmper1 read: bit 7 6 5 4 3 2 1 bit 0 write: $02d6 pwmper2 read: bit 7 6 5 4 3 2 1 bit 0 write: $02d7 pwmper3 read: bit 7 6 5 4 3 2 1 bit 0 write: $02d8 pwmper4 read: bit 7 6 5 4 3 2 1 bit 0 write: device user guide ?9s12kt256dgv1/d v01.09 51 freescale semiconductor 1.8 part id assignments the part id is located in two 8-bit registers partidh and partidl (addresses $001a and $001b after reset. the read-only value is a unique part id for each revision of the chip. table 1-4 assigned part id numbers shows the assigned part id number. $02d9 pwmper5 read: bit 7 6 5 4 3 2 1 bit 0 write: $02da pwmper6 read: bit 7 6 5 4 3 2 1 bit 0 write: $02db pwmper7 read: bit 7 6 5 4 3 2 1 bit 0 write: $02dc pwmdty0 read: bit 7 6 5 4 3 2 1 bit 0 write: $02dd pwmdty1 read: bit 7 6 5 4 3 2 1 bit 0 write: $02de pwmdty2 read: bit 7 6 5 4 3 2 1 bit 0 write: $02df pwmdty3 read: bit 7 6 5 4 3 2 1 bit 0 write: $02e0 pwmdty4 read: bit 7 6 5 4 3 2 1 bit 0 write: $02e1 pwmdty5 read: bit 7 6 5 4 3 2 1 bit 0 write: $02e2 pwmdty6 read: bit 7 6 5 4 3 2 1 bit 0 write: $02e3 pwmdty7 read: bit 7 6 5 4 3 2 1 bit 0 write: $02e4 pwmsdn read: pwmif pwmie pwmrs trt pwmlvl 0 pwm7in pwm7in l pwm7e na write: $02e5 reserved read: 0 0 0 0 0 0 0 0 write: $02e6 reserved read: 0 0 0 0 0 0 0 0 write: $02e7 reserved read: 0 0 0 0 0 0 0 0 write: $02e8 - $03ff reserved space address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $02e8 - $03ff reserved read: 0 0 0 0 0 0 0 0 write: $02c0 - $02e7 pwm (pulse width modulator 8 bit 8 channel) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device user guide ?9s12kt256dgv1/d v01.09 52 freescale semiconductor the device memory sizes are located in two 8-bit registers memsiz0 and memsiz1 (addresses $001c and $001d after reset). table 1-5 shows the read-only values of these registers. refer to hcs12 module mapping and control (mmc) block guide for further details. table 1-4 assigned part id numbers device mask set number part id 1 notes : 1. the coding is as follows: bit 15-12: major family identifier bit 11-8: minor family identifier bit 7-4: major mask set revision number including fab transfers bit 3-0: minor - non full - mask set revision MC9S12KT256 0l33v $7000 mc9s12kg128 0l74n $7100 table 1-5 memory size registers device register name value MC9S12KT256 memsiz0 $25 MC9S12KT256 memsiz1 $81 mc9s12kg128 memsiz0 $13 mc9s12kg128 memsiz1 $80 device user guide ?9s12kt256dgv1/d v01.09 53 freescale semiconductor section 2 signal description 2.1 device pinout the mc9s12k-family and its derivatives are available in a 112-pin low profile quad flat pack (lqfp), a 100-pin low profile quad flat pack (lqfp), and a 80-pin quad flat pack (qfp). most pins perform two or more functions, as described in the signal descriptions. figure 2-1 , figure 2-2 and figure 2-3 show the pin assignments for different packages. device user guide ?9s12kt256dgv1/d v01.09 54 freescale semiconductor figure 2-1 pin assignments for 112 lqfp vrh vdda pad15/an15 pad07/an07 pad14/an14 pad06/an06 pad13/an13 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4/miso2 pp5/kwp5/pwm5/mosi2 pp6/kwp6/pwm6/ ss2 pp7/kwp7/pwm7/sck2 pk7/ ecs vddx vssx pm0/rxcan0 pm1/txcan0 pm2/ rxcan1 /rxcan0/miso0 pm3/ txcan1 /txcan0/ ss0 pm4/rxcan0/rxcan4/mosi0 pm5/txcan0/txcan4/sck0 pj6/kwj6/rxcan4/sda pj7/kwj7/txcan4/scl vregen ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 pm6/rxcan4 pm7/txcan4 vssa vrl ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 xaddr17/pk3 xaddr16/pk2 xaddr15/pk1 xaddr14/pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 xaddr19/pk5 xaddr18/pk4 kwj1/pj1 kwj0/pj0 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 ss2/kwh7/ph7 sck2/kwh6/ph6 mosi2/kwh5/ph5 miso2/kwh4/ph4 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test ss1/kwh3/ph3 sck1/kwh2/ph2 mosi1/kwh1/ph1 miso1/kwh0/ph0 lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 signals shown in bold are not available on the 80 pin package mc9s12k-family 112lqfp 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 signals shown in italic are only available in MC9S12KT256 device user guide ?9s12kt256dgv1/d v01.09 55 freescale semiconductor figure 2-2 pin assignments for 100 lqfp vrh vdda pad07/an07 pad06/an06 pad05/an05 pad12/an12 pad04/an04 pad11/an11 pad03/an03 pad10/an10 pad02/an02 pad09/an09 pad01/an01 pad08/an08 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4/miso2 pp5/kwp5/pwm5/mosi2 pp6/kwp6/pwm6/ ss2 pp7/kwp7/pwm7/sck2 vddx vssx pm0/rxcan0 pm1/txcan0 pm2/ rxcan1 /rxcan0/miso0 pm3/ txcan1 /txcan0/ ss0 pm4/rxcan0/rxcan4/mosi0 pm5/txcan0/txcan4/sck0 pj6/kwj6/rxcan4/sda pj7/kwj7/txcan4/scl vregen ps7/ ss0 ps6/sck0 ps5/mosi0 ps4/miso0 ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 vssa vrl ss1/pwm3/kwp3/pp3 sck1/pwm2/kwp2/pp2 mosi1/pwm1/kwp1/pp1 miso1/pwm0/kwp0/pp0 xaddr16/pk2 xaddr15/pk1 xaddr14/pk0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 kwj1/pj1 kwj0/pj0 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 kwh5/ph5 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test ss1/kwh3/ph3 sck1/kwh2/ph2 mosi1/kwh1/ph1 miso1/kwh0/ph0 lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 signals shown in bold are not available on the 80 pin package mc9s12k-family 100lqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 signals shown in italic are only available in MC9S12KT256 device user guide ?9s12kt256dgv1/d v01.09 56 freescale semiconductor figure 2-3 pin assignments for 80 qfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vrh vdda pad07/an07 pad06/an06 pad05/an05 pad04/an04 pad03/an03 pad02/an02 pad01/an01 pad00/an00 vss2 vdd2 pa7/addr15/data15 pa6/addr14/data14 pa5/addr13/data13 pa4/addr12/data12 pa3/addr11/data11 pa2/addr10/data10 pa1/addr9/data9 pa0/addr8/data8 pp4/kwp4/pwm4/miso2 pp5/kwp5/pwm5/mosi2 pp7/kwp7/pwm7 sck2 vddx vssx pm0/rxcan0 pm1/txcan0 pm2/ rxcan1 /rxcan0/miso0 pm3/ txcan1 /txcan0/ ss0 pm4/rxcan0/rxcan4/mosi0 pm5/txcan0/txcan4/sck0 pj6/kwj6/rxcan4/sda pj7/kwj7/txcan4/scl vregen ps3/txd1 ps2/rxd1 ps1/txd0 ps0/rxd0 vssa vrl pwm3/kwp3/pp3 pwm2/kwp2/pp2 pwm1/kwp1/pp1 pwm0/kwp0/pp0 ioc0/pt0 ioc1/pt1 ioc2/pt2 ioc3/pt3 vdd1 vss1 ioc4/pt4 ioc5/pt5 ioc6/pt6 ioc7/pt7 modc/ t a ghi/bkgd addr0/data0/pb0 addr1/data1/pb1 addr2/data2/pb2 addr3/data3/pb3 addr4/data4/pb4 addr5/data5/pb5 addr6/data6/pb6 addr7/data7/pb7 xclks/noacc/pe7 modb/ipipe1/pe6 moda/ipipe0/pe5 eclk/pe4 vssr vddr reset vddpll xfc vsspll extal xtal test lstrb/ t a glo/pe3 r/ w/pe2 irq/pe1 xirq/pe0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 mc9s12k-family 80 qfp signals shown in italic are only available in MC9S12KT256 device user guide ?9s12kt256dgv1/d v01.09 57 freescale semiconductor 2.2 signal properties summary (table 2-1) summarizes the pin functionality. signals shown in bold are not available in the 80 pin package. (table 2-2) summarizes the power and ground pins. table 2-1 signal properties pin name function 1 pin name function 2 pin name function 3 pin name function 4 powered by internal pull resistor description ctrl reset state extal vddpll na na oscillator pins xtal vddpll na na reset vddr none none external reset test na na na test input vregen vddx na na voltage regulator enable input xfc vddpll na na pll loop filter bkgd t a ghi modc vddr always up up background debug, tag high, mode input pad[15:8] an[15:8] an1[7:0] 1 vdda none none port ad input, analog inputs of atd in mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64); analog inputs of atd1 in MC9S12KT256 and mc9s12kg256 pad[7:0] an[7:0] an0[7:0] 1 vdda none none port ad input, analog inputs of atd in mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64); analog inputs of atd0 in MC9S12KT256 and mc9s12kg256 pa[7:0] addr[15:8]/ data[15:8] vddr pucr disabled port a i/o, multiplexed address/data pb[7:0] addr[7:0]/ data[7:0] vddr pucr disabled port b i/o, multiplexed address/data pe7 noacc xclks vddr pucr up port e i/o, access, clock select pe6 ipipe1 modb vddr while reset pin is low: down port e i/o, pipe status, mode input pe5 ipipe0 moda vddr while reset pin is low: down port e i/o, pipe status, mode input pe4 eclk vddr pucr up port e i/o, bus clock output pe3 lstrb t a glo vddr pucr up port e i/o, byte strobe, tag low pe2 r/ w vddr pucr up port e i/o, r/ w in expanded modes pe1 irq vddr always up port e input, maskable interrupt pe0 xirq vddr port e input, non maskable interrupt ph7 kwh7 ss2 vddr perh/ ppsh disabled port h i/o, interrupt, ss of spi2 device user guide ?9s12kt256dgv1/d v01.09 58 freescale semiconductor ph6 kwh6 sck2 vddr perh/ ppsh disabled port h i/o, interrupt, sck of spi2 ph5 kwh5 mosi2 vddr perh/ ppsh disabled port h i/o, interrupt, mosi of spi2 ph4 kwh4 miso2 vddr perh/ ppsh disabled port h i/o, interrupt, miso of spi2 ph3 kwh3 ss1 vddr perh/ ppsh disabled port h i/o, interrupt, ss of spi1 ph2 kwh2 sck1 vddr perh/ ppsh disabled port h i/o, interrupt, sck of spi1 ph1 kwh1 mosi1 vddr perh/ ppsh disabled port h i/o, interrupt, mosi of spi1 ph0 kwh0 miso1 vddr perh/ ppsh disabled port h i/o, interrupt, miso of spi1 pj7 kwj7 txcan4 scl vddx perj/ ppsj up port j i/o, interrupt, tx of can4, scl of iic pj6 kwj6 rxcan4 sda vddx perj/ ppsj up port j i/o, interrupt, rx of can4, sda of iic pj[1:0] kwj[1:0] vddx perj/ ppsj up port j i/o, interrupts pk7 ecs romctl vddx pucr up port k i/o, emulation chip select, rom on enable pk[5:0] xaddr[19:14] vddx pucr up port k i/o, extended addresses pm7 txcan4 vddx perm/ ppsm disabled port m i/o, can4 tx pm6 rxcan4 vddx perm/ ppsm disabled port m i/o, can4 rx pm5 txcan0 txcan4 sck0 vddx perm/ ppsm disabled port m i/o, can0 tx, can4 tx, spi0 sck pm4 rxcan0 rxcan4 mosi0 vddx perm/ ppsm disabled port m i/o, can0 rx, can4 rx, spi0 mosi pm3 txcan1 1 txcan0 ss0 vddx perm/ ppsm disabled port m i/o, can1 tx, can0 tx, spi0 ss pm2 rxcan1 1 rxcan0 miso0 vddx perm/ ppsm disabled port m i/o, can1 rx, can0 rx, spi0 miso pm1 txcan0 vddx perm/ ppsm disabled port m i/o, can0 tx pm0 rxcan0 vddx perm/ ppsm disabled port m i/o, can0 rx pp7 kwp7 pwm7 sck2 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 7, sck of spi2 pp6 kwp6 pwm6 ss2 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 6, spi2 ss pp5 kwp5 pwm5 mosi2 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 5, spi2 mosi pp4 kwp4 pwm4 miso2 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 4, spi2 miso pin name function 1 pin name function 2 pin name function 3 pin name function 4 powered by internal pull resistor description ctrl reset state device user guide ?9s12kt256dgv1/d v01.09 59 freescale semiconductor table 2-2 power and ground pp3 kwp3 pwm3 ss1 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 3, spi1 ss pp2 kwp2 pwm2 sck1 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 2, spi1 sck pp1 kwp1 pwm1 mosi1 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 1, spi1 mosi pp0 kwp0 pwm0 miso1 vddx perp/ ppsp disabled port p i/o, interrupt, pwm channel 0, spi1 miso ps7 ss0 vddx pers/ ppss up port s i/o, spi0 ss ps6 sck0 vddx pers/ ppss up port s i/o, spi0 sck ps5 mosi0 vddx pers/ ppss up port s i/o, spi0 mosi ps4 miso0 vddx pers/ ppss up port s i/o, spi0 miso ps3 txd1 vddx pers/ ppss up port s i/o, sci1txd ps2 rxd1 vddx pers/ ppss up port s i/o, sci1rxd ps1 txd0 vddx pers/ ppss up port s i/o, sci0 txd ps0 rxd0 vddx pers/ ppss up port s i/o, sci0 rxd pt[7:0] ioc[7:0] vddx up or down disabled port t i/o, timer channels notes : 1. only available on MC9S12KT256. mnemonic nominal voltage description vdd1 vdd2 2.5 v internal power and ground generated by internal regulator. these also allow an external source to supply the core vdd/vss voltages and bypass the internal voltage regulator. vss1 vss2 0v vddr 3.3/5.0 v external power and ground, supply to pin drivers and internal voltage regulator. vssr 0 v vddx 3.3/5.0 v external power and ground, supply to pin drivers. vssx 0 v vdda 3.3/5.0 v operating voltage and ground for the analog-to-digital converter and the reference for the internal voltage regulator, allows the supply voltage to the a/d to be bypassed independently. vssa 0 v vrh 3.3/5.0 v reference voltage high for the atd converter. vrl 0 v reference voltage low for the atd converter. pin name function 1 pin name function 2 pin name function 3 pin name function 4 powered by internal pull resistor description ctrl reset state device user guide ?9s12kt256dgv1/d v01.09 60 freescale semiconductor note: all vss pins must be connected together in the application. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on mcu pin load. 2.3 detailed signal descriptions 2.3.1 extal, xtal ?oscillator pins extal and xtal are the crystal driver and external clock pins. on reset all the device clocks are derived from the extal input frequency. xtal is the crystal output. 2.3.2 reset ?external reset pin an active low bidirectional control signal, it acts as an input to initialize the mcu to a known start-up state, and an output when an internal mcu function causes a reset. 2.3.3 test ?test pin this input only pin is reserved for test. note: the test pin must be tied to vss in all applications. 2.3.4 vregen ?voltage regulator enable pin this input only pin enables or disables the on-chip voltage regulator. vddpll 2.5 v provides operating voltage and ground for the phased-locked loop. this allows the supply voltage to the pll to be bypassed independently. internal power and ground generated by internal regulator. vsspll 0 v mnemonic nominal voltage description device user guide ?9s12kt256dgv1/d v01.09 61 freescale semiconductor 2.3.5 xfc ?pll loop filter pin pll loop filter. please ask your motorola representative for the interactive application note to compute pll loop filter elements. any current leakage on this pin must be avoided. figure 2-4 pll loop filter connections 2.3.6 bkgd / taghi / modc ?background debug, tag high, and mode pin the bkgd/ taghi /modc pin is used as a pseudo-open-drain pin for the background debug communication. in mcu expanded modes of operation when instruction tagging is on, an input low on this pin during the falling edge of e-clock tags the high half of the instruction word being read into the instruction queue. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modc bit at the rising edge of reset . 2.3.7 pad[15:8] / an[15:8] ?port ad input pins [15:8] pad15 - pad8 are general purpose input pins and analog inputs of the single analog to digital converter with 16 channels on mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64). pad15 - pad8 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels (atd1) on MC9S12KT256 and mc9s12kg256. 2.3.8 pad[7:0] / an[7:0] ?port ad input pins [7:0] pad7 - pad0 are general purpose input pins and analog inputs of the single analog to digital converter with 16 channels on mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64). pad7 - pad0 are general purpose input pins and analog inputs of the analog to digital converter with 8 channels (atd0) on MC9S12KT256 and mc9s12kg256. 2.3.9 pa[7:0] / addr[15:8] / data[15:8] ?port a i/o pins pa7-pa0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. mcu xfc r c s c p vddpll vddpll device user guide ?9s12kt256dgv1/d v01.09 62 freescale semiconductor 2.3.10 pb[7:0] / addr[7:0] / data[7:0] ?port b i/o pins pb7-pb0 are general purpose input or output pins. in mcu expanded modes of operation, these pins are used for the multiplexed external address and data bus. 2.3.11 pe7 / noacc / xclks ?port e i/o pin 7 pe7 is a general purpose input or output pin. during mcu expanded modes of operation, the noacc signal, when enabled, is used to indicate that the current bus cycle is an unused or ?ree?cycle. this signal will assert when the cpu is not using the bus. the xclks is an input signal which controls whether a crystal in combination with the internal loop controlled pierce (low power) oscillator is used or whether full swing pierce oscillator/external clock circuitry is used. the state of this pin is latched at the rising edge of reset . if the input is a logic low the extal pin is configured for an external clock drive or full swing pierce oscillator. if input is a logic high a loop controlled pierce oscillator circuit is configured on extal and xtal. since this pin is an input with a pull-up device during reset, if the pin is left floating, the default configuration is a loop controlled pierce oscillator circuit on extal and xtal. figure 2-5 loop controlled pierce oscillator connections (pe7=1) table 2-3 clock selection based on pe7 during reset pe7 description 1 loop controlled pierce oscillator selected 0 full swing pierce oscillator or external clock selected mcu extal xtal vsspll crystal or ceramic resonator c 8 c 7 device user guide ?9s12kt256dgv1/d v01.09 63 freescale semiconductor figure 2-6 full swing pierce oscillator connections (pe7=0) figure 2-7 external clock connections (pe7=0) 2.3.12 pe6 / modb / ipipe1 ?port e i/o pin 6 pe6 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the modb bit at the rising edge of reset . this pin is shared with the instruction queue tracking signal ipipe1. 2.3.13 pe5 / moda / ipipe0 ?port e i/o pin 5 pe5 is a general purpose input or output pin. it is used as a mcu operating mode select pin during reset. the state of this pin is latched to the moda bit at the rising edge of reset . this pin is shared with the instruction queue tracking signal ipipe0. 2.3.14 pe4 / eclk ?port e i/o pin 4 pe4 is a general purpose input or output pin. it can be configured to drive the internal bus clock eclk. eclk can be used as a timing reference. * rs can be zero (shorted) when use with higher frequency crystals. refer to manufacturer? data. mcu extal xtal r s * r b vsspll crystal or ceramic resonator c 8 c 7 mcu extal xtal cmos-compatible external oscillator not connected (vddpll-level) device user guide ?9s12kt256dgv1/d v01.09 64 freescale semiconductor 2.3.15 pe3 / lstrb / taglo ?port e i/o pin 3 pe3 is a general purpose input or output pin. in mcu expanded modes of operation, lstrb can be used for the low-byte strobe function to indicate the type of bus access and when instruction tagging is on, taglo is used to tag the low half of the instruction word being read into the instruction queue. 2.3.16 pe2 / r/ w port e i/o pin 2 pe2 is a general purpose input or output pin. in mcu expanded modes of operations, this pin drives the read/write output signal for the external bus. it indicates the direction of data on the external bus. 2.3.17 pe1 / irq ?port e input pin 1 pe1 is a general purpose input pin and the maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.18 pe0 / xirq ?port e input pin 0 pe0 is a general purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. this will wake up the mcu from stop or wait mode. 2.3.19 ph7 / kwh7 / ss2 ?port h i/o pin 7 ph7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as slave select pin ss of the serial peripheral interface 2 (spi2). 2.3.20 ph6 / kwh6 / sck2 ?port h i/o pin 6 ph6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as serial clock pin sck of the serial peripheral interface 2 (spi2). 2.3.21 ph5 / kwh5 / mosi2 ?port h i/o pin 5 ph5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 2 (spi2). 2.3.22 ph4 / kwh4 / miso2 ?port h i/o pin 2 ph4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 2 (spi2). device user guide ?9s12kt256dgv1/d v01.09 65 freescale semiconductor 2.3.23 ph3 / kwh3 / ss1 ?port h i/o pin 3 ph3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as slave select pin ss of the serial peripheral interface 1 (spi1). 2.3.24 ph2 / kwh2 / sck1 ?port h i/o pin 2 ph2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as serial clock pin sck of the serial peripheral interface 1 (spi1). 2.3.25 ph1 / kwh1 / mosi1 ?port h i/o pin 1 ph1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 1 (spi1). 2.3.26 ph0 / kwh0 / miso1 ?port h i/o pin 0 ph0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 1 (spi1). 2.3.27 pj7 / kwj7 / txcan4 / scl ?port j i/o pin 7 pj7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the transmit pin txcan for the motorola scalable controller area network controller 4 (can4) or the serial clock pin scl of the iic module. 2.3.28 pj6 / kwj6 / rxcan4 / sda ?port j i/o pin 6 pj6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as the receive pin rxcan for the motorola scalable controller area network controller 4 (can4) or the serial data pin sda of the iic module. 2.3.29 pj[1:0] / kwj[1:0] ?port j i/o pins [1:0] pj1 and pj0 are general purpose input or output pins. they can be configured to generate an interrupt causing the mcu to exit stop or wait mode. 2.3.30 pk7 / ecs / romctl ?port k i/o pin 7 pk7 is a general purpose input or output pin. during mcu expanded modes of operation, this pin is used as the emulation chip select output ( ecs ). during mcu expanded modes of operation, this pin is used to device user guide ?9s12kt256dgv1/d v01.09 66 freescale semiconductor enable the flash eeprom memory in the memory map (romctl). at the rising edge of reset , the state of this pin is latched to the romon bit.for all other modes the reset state of the romon bit is as follows: special single : romctl = 1 normal single : romctl = 1 emulation expanded wide : romctl = 0 emulation expanded narrow : romctl = 0 special test : romctl = 0 peripheral test : romctl = 1 2.3.31 pk[5:0] / xaddr[19:14] ?port k i/o pins [5:0] pk5-pk0 are general purpose input or output pins. in mcu expanded modes of operation, these pins provide the expanded address xaddr[19:14] for the external bus. 2.3.32 pm7 / txcan4 ?port m i/o pin 7 pm7 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 4 (can4). 2.3.33 pm6 / rxcan4 ?port m i/o pin 6 pm6 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 4 (can4). 2.3.34 pm5 / txcan0 / txcan4 / sck0 ?port m i/o pin 5 pm5 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 0 or 4 (can0 or can4). it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0). 2.3.35 pm4 / rxcan0 / rxcan4/ mosi0 ?port m i/o pin 4 pm4 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 0 or 4 (can0 or can4). it can be configured as the master output (during master mode) or slave input pin (during slave mode) mosi for the serial peripheral interface 0 (spi0). device user guide ?9s12kt256dgv1/d v01.09 67 freescale semiconductor 2.3.36 pm3 / txcan1 / txcan0 / ss0 ?port m i/o pin 3 pm3 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controllers 1 or 0 (can1 or can0). it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.3.37 pm2 / rxcan1 / rxcan0 / miso0 ?port m i/o pin 2 pm2 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controllers 1 or 0 (can1 or can0). it can be configured as the master input (during master mode) or slave output pin (during slave mode) miso for the serial peripheral interface 0 (spi0). 2.3.38 pm1 / txcan0 ?port m i/o pin 1 pm1 is a general purpose input or output pin. it can be configured as the transmit pin txcan of the motorola scalable controller area network controller 0 (can0). 2.3.39 pm0 / rxcan0 ?port m i/o pin 0 pm0 is a general purpose input or output pin. it can be configured as the receive pin rxcan of the motorola scalable controller area network controller 0 (can0). 2.3.40 pp7 / kwp7 / pwm7 / sck2 ?port p i/o pin 7 pp7 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 7 output. it can be configured as serial clock pin sck of the serial peripheral interface 2 (spi2). 2.3.41 pp6 / kwp6 / pwm6 / ss2 ?port p i/o pin 6 pp6 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 6 output. it can be configured as slave select pin ss of the serial peripheral interface 2 (spi2). 2.3.42 pp5 / kwp5 / pwm5 / mosi2 ?port p i/o pin 5 pp5 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 5 output. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 2 (spi2). device user guide ?9s12kt256dgv1/d v01.09 68 freescale semiconductor 2.3.43 pp4 / kwp4 / pwm4 / miso2 ?port p i/o pin 4 pp4 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 4 output. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 2 (spi2). 2.3.44 pp3 / kwp3 / pwm3 / ss1 ?port p i/o pin 3 pp3 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 3 output. it can be configured as slave select pin ss of the serial peripheral interface 1 (spi1). 2.3.45 pp2 / kwp2 / pwm2 / sck1 ?port p i/o pin 2 pp2 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 2 output. it can be configured as serial clock pin sck of the serial peripheral interface 1 (spi1). 2.3.46 pp1 / kwp1 / pwm1 / mosi1 ?port p i/o pin 1 pp1 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 1 output. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 1 (spi1). 2.3.47 pp0 / kwp0 / pwm0 / miso1 ?port p i/o pin 0 pp0 is a general purpose input or output pin. it can be configured to generate an interrupt causing the mcu to exit stop or wait mode. it can be configured as pulse width modulator (pwm) channel 0 output. it can be configured as master input (during master mode) or slave output (during slave mode) pin miso of the serial peripheral interface 1 (spi1). 2.3.48 ps7 / ss0 ?port s i/o pin 7 ps6 is a general purpose input or output pin. it can be configured as the slave select pin ss of the serial peripheral interface 0 (spi0). 2.3.49 ps6 / sck0 ?port s i/o pin 6 ps6 is a general purpose input or output pin. it can be configured as the serial clock pin sck of the serial peripheral interface 0 (spi0). device user guide ?9s12kt256dgv1/d v01.09 69 freescale semiconductor 2.3.50 ps5 / mosi0 ?port s i/o pin 5 ps5 is a general purpose input or output pin. it can be configured as master output (during master mode) or slave input pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.3.51 ps4 / miso0 ?port s i/o pin 4 ps4 is a general purpose input or output pin. it can be configured as master input (during master mode) or slave output pin (during slave mode) mosi of the serial peripheral interface 0 (spi0). 2.3.52 ps3 / txd1 ?port s i/o pin 3 ps3 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 1 (sci1). 2.3.53 ps2 / rxd1 ?port s i/o pin 2 ps2 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 1 (sci1). 2.3.54 ps1 / txd0 ?port s i/o pin 1 ps1 is a general purpose input or output pin. it can be configured as the transmit pin txd of serial communication interface 0 (sci0). 2.3.55 ps0 / rxd0 ?port s i/o pin 0 ps0 is a general purpose input or output pin. it can be configured as the receive pin rxd of serial communication interface 0 (sci0). 2.3.56 pt[7:0] / ioc[7:0] ?port t i/o pins [7:0] pt7-pt0 are general purpose input or output pins. they can be configured as input capture or output compare pins ioc7-ioc0 of the timer (tim). 2.4 power supply pins mc9s12k-family power and ground pins are described below. note: all vss pins must be connected together in the application. device user guide ?9s12kt256dgv1/d v01.09 70 freescale semiconductor 2.4.1 vddx,vssx ?power supply pins for i/o drivers external power and ground for i/o drivers. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 2.4.2 vddr, vssr ?power supply pins for i/o drivers & for internal voltage regulator external power and ground for i/o drivers and input to the internal voltage regulator. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. bypass requirements depend on how heavily the mcu pins are loaded. 2.4.3 vdd1, vdd2, vss1, vss2 ?power supply pins for internal logic power is supplied to the mcu through vdd and vss. because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the mcu as possible. this 2.5v supply is derived from the internal voltage regulator. there is no static load on those pins allowed. the internal voltage regulator is turned off, if vregen is tied to ground. note: no load allowed except for bypass capacitors. 2.4.4 vdda, vssa ?power supply pins for atd and vreg vdda, vssa are the power supply and ground input pins for the voltage regulator and the analog to digital converter. it also provides the reference for the internal voltage regulator. this allows the supply voltage to the atd and the reference voltage to be bypassed independently. 2.4.5 vrh, vrl ?atd reference voltage input pins vrh and vrl are the reference voltage input pins for the analog to digital converter. 2.4.6 vddpll, vsspll ?power supply pins for pll provides operating voltage and ground for the oscillator and the phased-locked loop. this allows the supply voltage to the oscillator and pll to be bypassed independently. this 2.5v voltage is generated by the internal voltage regulator. note: no load allowed except for bypass capacitors. device user guide ?9s12kt256dgv1/d v01.09 71 freescale semiconductor section 3 system clock description the clock and reset generator provides the internal clock signals for the core and all peripheral modules. figure 3-1 shows the clock connections from the crg to all modules. consult the crg block guide for details on clock generation. figure 3-1 clock connections crg bus clock core clock extal xtal oscillator clock hcs12 core flash bdm osc cpu mebi mmc int dbg iic ram sci0, sci1 pwm atd eeprom tim spi0, spi1, spi2 can0, can1, can4 pim device user guide ?9s12kt256dgv1/d v01.09 72 freescale semiconductor section 4 modes of operation 4.1 overview eight possible modes determine the operating configuration of the mc9s12k-family. each mode has an associated default memory map and external bus configuration controlled by a further pin. three low power modes exist for the device. 4.2 chip configuration summary the operating mode out of reset is determined by the states of the modc, modb, and moda pins during reset ( (table 4-1) ). the modc, modb, and moda bits in the mode register show the current operating mode and provide limited mode switching during operation. the states of the modc, modb, and moda pins are latched into these bits on the rising edge of the reset signal. the romctl signal allows the setting of the romon bit in the misc register thus controlling whether the internal flash is visible in the memory map. romon = 1 mean the flash is visible in the memory map. the state of the romctl pin is latched into the romon bit in the misc register on the rising edge of the reset signal. for further explanation on the modes refer to the hcs12 mebi block guide. table 4-1 mode selection bkgd = modc pe6 = modb pe5 = moda pk7 = romctl romon bit mode description 0 0 0 x 1 special single chip, bdm allowed and active . bdm is allowed in all other modes but a serial command is required to make bdm active . 0 0 1 0 1 emulation expanded narrow, bdm allowed 1 0 0 1 0 x 0 special test (expanded wide), bdm allowed 0 1 1 0 1 emulation expanded wide, bdm allowed 1 0 1 0 0 x 1 normal single chip, bdm allowed 1 0 1 0 0 normal expanded narrow, bdm allowed 1 1 1 1 0 x 1 peripheral; bdm allowed but bus operations would cause bus con?cts (must not be used) 1 1 1 0 0 normal expanded wide, bdm allowed 1 1 device user guide ?9s12kt256dgv1/d v01.09 73 freescale semiconductor 4.3 security the device will make available a security feature preventing the unauthorized read and write of the memory contents. this feature allows: protection of the contents of flash, protection of the contents of eeprom, operation in single-chip mode, operation from external memory with internal flash and eeprom disabled. the user must be reminded that part of the security must lie with the user? code. an extreme example would be user? code that dumps the contents of the internal program. this code would defeat the purpose of security. at the same time the user may also wish to put a back door in the user? program. an example of this is the user downloads a key through the sci which allows access to a programming routine that updates parameters stored in eeprom. 4.3.1 securing the microcontroller once the user has programmed the flash and eeprom (if desired), the part can be secured by programming the security bits located in the flash module. these non-volatile bits will keep the part secured through resetting the part and through powering down the part. the security byte resides in a portion of the flash array. check the flash block guide for more details on the security configuration. table 4-2 clock selection based on pe7 pe7 = xclks description 1 loop controlled pierce oscillator selected 0 full swing pierce oscillator or external clock selected table 4-3 voltage regulator vregen vregen description 1 internal voltage regulator enabled 0 internal voltage regulator disabled, vdd1,2 and vddpll must be supplied externally with 2.5v device user guide ?9s12kt256dgv1/d v01.09 74 freescale semiconductor 4.3.2 operation of the secured microcontroller 4.3.2.1 normal single chip mode this will be the most common usage of the secured part. everything will appear the same as if the part was not secured with the exception of bdm operation. the bdm operation will be blocked. 4.3.2.2 executing from external memory the user may wish to execute from external space with a secured microcontroller. this is accomplished by resetting directly into expanded mode. the internal flash and eeprom will be disabled. bdm operations will be blocked. 4.3.3 unsecuring the microcontroller in order to unsecure the microcontroller, the internal flash and eeprom must be erased. this can be done through an external program in expanded mode. once the user has erased the flash and eeprom, the part can be reset into special single chip mode. this invokes a program that verifies the erasure of the internal flash and eeprom. once this program completes, the user can erase and program the flash security bits to the unsecured state. this is generally done through the bdm, but the user could also change to expanded mode (by writing the mode bits through the bdm) and jumping to an external program (again through bdm commands). note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be secured again. 4.4 low power modes the microcontroller features three main low power modes. consult the respective block guide for information on the module behavior in stop, pseudo stop, and wait mode. an important source of information about the clock system is the clock and reset generator guide (crg). 4.4.1 stop executing the cpu stop instruction stops all clocks and the oscillator thus putting the chip in fully static mode. wake up from this mode can be done via reset or external interrupts. 4.4.2 pseudo stop this mode is entered by executing the cpu stop instruction. in this mode the oscillator is still running and the real time interrupt (rti) or watchdog (cop) sub module can stay active. other peripherals are turned off. this mode consumes more current than the full stop mode, but the wake up time from this mode is significantly shorter. device user guide ?9s12kt256dgv1/d v01.09 75 freescale semiconductor 4.4.3 wait this mode is entered by executing the cpu wai instruction. in this mode the cpu will not execute instructions. the internal cpu signals (address and databus) will be fully static. all peripherals stay active. for further power consumption the peripherals can individually turn off their local clocks. 4.4.4 run although this is not a low power mode, unused peripheral modules should not be enabled in order to save power. device user guide ?9s12kt256dgv1/d v01.09 76 freescale semiconductor section 5 resets and interrupts 5.1 overview consult the exception processing section of the cpu12 reference manual for information on resets and interrupts. both local masking and ccr masking are included as listed in table 5-1 . system resets can be generated through external control of the reset pin, through the clock and reset generator module crg or through the low voltage reset (lvr) generator of the voltage regulator module. refer to the crg and vreg block guides for detailed information on reset generation. 5.2 vectors 5.2.1 vector table (table 5-1) lists interrupt sources and vectors in default order of priority. table 5-1 interrupt vector locations vector address interrupt source ccr mask local enable hprio value to elevate $fffe, $ffff external reset, power on reset or low voltage reset (see crg flags register to determine reset source) none none $fffc, $fffd clock monitor fail reset none pllctl (cme, fcme) $fffa, $fffb cop failure reset none cop rate select $fff8, $fff9 unimplemented instruction trap none none $fff6, $fff7 swi none none $fff4, $fff5 xirq x-bit none $fff2, $fff3 irq i-bit irqcr (irqen) $f2 $fff0, $fff1 real time interrupt i-bit crgint (rtie) $f0 $ffee, $ffef standard timer channel 0 i-bit tie (c0i) $ee $ffec, $ffed standard timer channel 1 i-bit tie (c1i) $ec $ffea, $ffeb standard timer channel 2 i-bit tie (c2i) $ea $ffe8, $ffe9 standard timer channel 3 i-bit tie (c3i) $e8 $ffe6, $ffe7 standard timer channel 4 i-bit tie (c4i) $e6 $ffe4, $ffe5 standard timer channel 5 i-bit tie (c5i) $e4 $ffe2, $ffe3 standard timer channel 6 i-bit tie (c6i) $e2 $ffe0, $ffe1 standard timer channel 7 i-bit tie (c7i) $e0 $ffde, $ffdf standard timer over?w i-bit tscr2 (toi) $de $ffdc, $ffdd pulse accumulator over?w i-bit pactl (paovi) $dc $ffda, $ffdb pulse accumulator input edge i-bit pactl (pai) $da $ffd8, $ffd9 spi0 i-bit spicr1 (spie, sptie) $d8 $ffd6, $ffd7 sci0 i-bit scicr2 (tie, tcie, rie, ilie) $d6 $ffd4, $ffd5 sci1 i-bit scicr2 (tie, tcie, rie, ilie) $d4 $ffd2, $ffd3 atd0 i-bit atdctl2 (ascie) $d2 device user guide ?9s12kt256dgv1/d v01.09 77 freescale semiconductor $ffd0, $ffd1 atd1 i-bit atdctl2 (ascie) 1 $d0 $ffce, $ffcf port j i-bit piej (piej7, piej6, piej1, piej0) $ce $ffcc, $ffcd port h i-bit pieh (pieh7-0) $cc $ffca, $ffcb reserved i-bit reserved $ca $ffc8, $ffc9 i-bit $c8 $ffc6, $ffc7 crg pll lock i-bit crgint (lockie) $c6 $ffc4, $ffc5 crg self clock mode i-bit crgint (scmie) $c4 $ffc2, $ffc3 flash double fault detect i-bit fcnfg (dfdie) $c2 $ffc0, $ffc1 iic bus i-bit ibcr (ibie) $c0 $ffbe, $ffbf spi1 i-bit spicr1 (spie, sptie) $be $ffbc, $ffbd spi2 i-bit spicr1 (spie, sptie) $bc $ffba, $ffbb eeprom command i-bit ecnfg (ccie, cbeie) $ba $ffb8, $ffb9 flash command i-bit fcnfg (ccie, cbeie) $b8 $ffb6, $ffb7 can0 wake-up i-bit can0rier (wupie) $b6 $ffb4, $ffb5 can0 errors i-bit can0rier (cscie, ovrie) $b4 $ffb2, $ffb3 can0 receive i-bit can0rier (rxfie) $b2 $ffb0, $ffb1 can0 transmit i-bit can0tier (txeie2 - txeie0) $b0 $ffae, $ffaf can1 wake-up i-bit can1rier (wupie) 1 $ae $ffac, $ffad can1 errors i-bit can1rier (cscie, ovrie) 1 $ac $ffaa, $ffab can1 receive i-bit can1rier (rxfie) 1 $aa $ffa8, $ffa9 can1 transmit i-bit can1tier (txeie2 - txeie0) 1 $a8 $ffa6, $ffa7 reserved i-bit reserved $a6 $ffa4, $ffa5 i-bit $a4 $ffa2, $ffa3 i-bit $a2 $ffa0, $ffa1 i-bit $a0 $ff9e, $ff9f i-bit $9e $ff9c, $ff9d i-bit $9c $ff9a, $ff9b i-bit $9a $ff98, $ff99 i-bit $98 $ff96, $ff97 can4 wake-up i-bit can4rier (wupie) $96 $ff94, $ff95 can4 errors i-bit can4rier (cscie, ovrie) $94 $ff92, $ff93 can4 receive i-bit can4rier (rxfie) $92 $ff90, $ff91 can4 transmit i-bit can4tier (txeie2 - txeie0) $90 $ff8e, $ff8f port p i-bit piep (piep7-0) $8e $ff8c, $ff8d pwm emergency shutdown i-bit pwmsdn (pwmie) $8c $ff8a, $ff8b vreg low voltage interrupt i-bit ctrl0 (lvie) $8a $ff80 to $ff89 reserved notes : 1. interrupt vector is only available on MC9S12KT256. otherwise it is reserved. device user guide ?9s12kt256dgv1/d v01.09 78 freescale semiconductor 5.3 resets resets are a subset of the interrupts featured in table 5-1 . the different sources capable of generating a system reset are summarized in table 5-2 . 5.3.1 effects of reset when a reset occurs, mcu registers and control bits are changed to known start-up states. refer to the respective module block guides for register reset states. refer to the hcs12 mebi block guide for mode dependent pin configuration of port a, b and e out of reset. refer to the pim block guide for reset configurations of all peripheral module ports. refer to table 1-2 (table 1-2) for locations of the memories depending on the operating mode after reset. the ram array is not automatically initialized out of reset. section 6 hcs12 core block description 6.1 cpu12 block description consult the cpu12 reference manual for information about the central processing unit. when the cpu12 reference manual refers to cycles this is equivalent to bus clock periods . so 1 cycle is equivalent to 1 bus clock period . 6.2 hcs12 background debug module (bdm) block description consult the hcs12 bdm block guide for information about the background debug module. when the bdm block guide refers to alternate clock this is equivalent to oscillator clock . table 5-2 reset summary reset priority source vector power-on reset 1 crg module $fffe, $ffff external reset 1 reset pin $fffe, $ffff low voltage reset 1 vreg module $fffe, $ffff clock monitor reset 2 crg module $fffc, $fffd cop watchdog reset 3 crg module $fffa, $fffb device user guide ?9s12kt256dgv1/d v01.09 79 freescale semiconductor 6.3 hcs12 debug (dbg) block description consult the hcs12 dbg block guide for information about the debug module. 6.4 hcs12 interrupt (int) block description consult the hcs12 int block guide for information about the interrupt module. 6.5 hcs12 multiplexed external bus interface (mebi) block description consult the hcs12 mebi block guide for information about the multiplexed external bus interface module. 6.6 hcs12 module mapping control (mmc) block description consult the hcs12 mmc block guide for information about the module mapping control module. section 7 analog to digital converter (atd) block description consult the atd_10b16c block guide for further information about the a/d converter module for the mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64). when the atd_10b16c block guide refers to freeze mode this is equivalent to active bdm mode. consult the atd_10b8c block guide for further information about the a/d converter module for the MC9S12KT256 and mc9s12kg256. when the atd_10b8c block guide refers to freeze mode this is equivalent to active bdm mode. section 8 clock reset generator (crg) block description consult the crg block guide for information about the clock and reset generator module. 8.1 device-specific information the low voltage reset feature uses the low voltage reset signal from the vreg module as an input to the crg module. when the regulator output voltage supply to the internal chip logic falls below a specified threshold the lvr signal from the vreg module causes the crg module to generate a reset. consult the vreg block guide for voltage level specifications. device user guide ?9s12kt256dgv1/d v01.09 80 freescale semiconductor section 9 eeprom block description consult the eets2k block guide for information about the eeprom module for the mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64). consult the eets4k block guide for information about the eeprom module for the MC9S12KT256 and mc9s12kg256. section 10 flash eeprom block description consult the fts128k1ecc block guide for information about the flash module for the mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64). consult the fts256k2ecc block guide for information about the flash module for the MC9S12KT256 and mc9s12kg256. the "s12 lrae" is a generic load ram and execute (lrae) program which will be programmed into the flash memory of this device during manufacture. this lrae program will provide greater programming flexibility to the end users by allowing the device to be programmed directly using sci after it is assembled on the pcb. use of the lrae program is at the discretion of the end user and, if not required, it must simply be erased prior to flash programming. for more details of the s12 lrae and its implementation, please see the s12 lrea application note (an2546/d) . it is planned that most hc9s12 devices manufactured after q1 of 2004 will be shipped with the s12 lrae programmed in the flash . exact details of the changeover (ie blank to programmed) for each product will be communicated in advance via gpcn and will be traceable by the customer via datecode marking on the device. please contact motorola sps sales if you have any additional questions. section 11 iic block description consult the iic block guide for information about the inter-ic bus module. section 12 mscan block description there are three mscan modules (can4, can1 and can0) implemented on the MC9S12KT256. there are only two mscan modules (can4 and can0) implemented on the mc9s12kg128(64)(32). there is only one mscan module (can0) implemented on the mc9s12kl128(64) and mc9s12kc128(64). consult the mscan block guide for information about the motorola scalable can module. section 13 osc block description device user guide ?9s12kt256dgv1/d v01.09 81 freescale semiconductor consult the osc_lcp block guide for information about the oscillator module. section 14 port integration module (pim) block description consult the pim_9kg128 block guide for information about the port integration module for the mc9s12kg128(64)(32), mc9s12kl128(64) and mc9s12kc128(64). consult the pim_9kt256 block guide for information about the port integration module for the MC9S12KT256 and mc9s12kg256. section 15 pulse width modulator (pwm) block description consult the pwm_8b8c block guide for information about the pulse width modulator module. when the pwm_8b8c block guide refers to freeze mode this is equivalent to active bdm mode. section 16 serial communications interface (sci) block description there are two serial communications interface modules (sci1 and sci0). consult the sci block guide for information about the serial communications interface module. section 17 serial peripheral interface (spi) block description there are three serial peripheral interfaces (spi2, spi1 and spi0) implemented on mc9s12k-family. consult the spi block guide for information about each serial peripheral interface module. section 18 timer (tim) block description consult the tim_16b8c block guide for information about the timer module. when the tim_16b8c block guide refers to freeze mode this is equivalent to active bdm mode. section 19 voltage regulator (vreg) block description consult the vreg_3v3 block guide for information about the dual output linear voltage regulator. device user guide ?9s12kt256dgv1/d v01.09 82 freescale semiconductor 19.1 device-specific information 19.1.1 vdd1, vdd2, vss1, vss2 in all package versions, both internal vdd and vss of the 2.5v domain are bonded out on 2 sides of the device as two pin pairs (vdd1, vss1 & vdd2, vss2). vdd1 and vdd2 are connected together internally. vss1 and vss2 are connected together internally. this allows systems to employ better supply routing and further decoupling. device user guide ?9s12kt256dgv1/d v01.09 83 freescale semiconductor appendix a electrical characteristics a.1 general note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values cannot be guaranteed by motorola and are subject to change without notice. this supplement contains the most accurate electrical information for the mc9s12k-family of microcontrollers available at the time of publication. the information should be considered preliminary and is subject to change. this introduction is intended to give an overview on several common topics like power supply, current injection etc. a.1.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate. note: this classification is shown in the column labeled ??in the parameter tables where appropriate. p: those parameters are guaranteed during production testing on each individual device. c: those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. they are regularly verified by production monitors. t: those parameters are achieved by design characterization on a small sample size from typical devices. all values shown in the typical column are within this category. d: those parameters are derived mainly from simulations. a.1.2 power supply the mc9s12k-family utilizes several pins to supply power to the i/o ports, a/d converter, oscillator, pll and internal logic. the vdda, vssa pair supplies the a/d converter. the vddx, vssx pair supplies the i/o pins device user guide ?9s12kt256dgv1/d v01.09 84 freescale semiconductor the vddr, vssr pair supplies the internal voltage regulator. vdd1, vss1, vdd2 and vss2 are the supply pins for the digital logic. vddpll, vsspll supply the oscillator and the pll. vss1 and vss2 are internally connected by metal. vdd1 and vdd2 are internally connected by metal. vdda, vddx, vddr as well as vssa, vssx, vssr are connected by anti-parallel diodes for esd protection. note: in the following context vdd5 is used for either vdda, vddr and vddx; vss5 is used for either vssa, vssr and vssx unless otherwise noted. idd5 denotes the sum of the currents flowing into the vdda, vddx and vddr pins. vdd is used for vdd1, vdd2 and vddpll, vss is used for vss1, vss2 and vsspll. idd is used for the sum of the currents flowing into vdd1 and vdd2. a.1.3 pins there are four groups of functional pins. a.1.3.1 3.3v/5v i/o pins those i/o pins have a nominal level of 3.3v or 5v depending on the application operating point. this group of pins is comprised of all port i/o pins, the analog inputs, bkgd pin and the reset inputs.the internal structure of all those pins is identical, however some of the functionality may be disabled. e.g. for the analog inputs the output drivers, pull-up and pull-down resistors are disabled permanently. a.1.3.2 analog reference this group of pins is comprised of the vrh and vrl pins. a.1.3.3 oscillator the pins extal, xtal dedicated to the oscillator have a nominal 2.5v level. they are supplied by vddpll. a.1.3.4 pll the pin xfc dedicated to the oscillator have a nominal 2.5v level. it is supplied by vddpll. a.1.3.5 test this pin is used for production testing only. a.1.4 current injection power supply must maintain regulation within operating v dd5 or v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd5 ) is greater than i dd5 , the injection current may flow out of vdd5 and could result in external power supply going out of regulation. device user guide ?9s12kt256dgv1/d v01.09 85 freescale semiconductor insure external vdd5 load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power; e.g. if no system clock is present, or if clock rate is very low which would reduce overall power consumption. a.1.5 absolute maximum ratings absolute maximum ratings are stress ratings only. a functional operation under or outside those maxima is not guaranteed. stress beyond those limits may affect the reliability or cause permanent damage of the device. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss5 or v dd5 ). table a-1 absolute maximum ratings num rating symbol min max unit 1 i/o, regulator and analog supply voltage v dd5 -0.3 6.5 v 2 internal logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when the device is powered from an external source. v dd -0.3 3.0 v 3 pll supply voltage (1) v ddpll -0.3 3.0 v 4 voltage difference vddx to vddr and vdda ? vddx -0.3 0.3 v 5 voltage difference vssx to vssr and vssa ? vssx -0.3 0.3 v 6 digital i/o input voltage v in -0.3 6.5 v 7 analog reference v rh, v rl -0.3 6.5 v 8 xfc, extal, xtal inputs v ilv -0.3 3.0 v 9 test input v test -0.3 10.0 v 10 instantaneous maximum current single pin limit for all digital i/o pins 2 2. all digital i/o pins are internally clamped to v ssx and v ddx , v ssr and v ddr or v ssa and v dda . i d -25 +25 ma 11 instantaneous maximum current single pin limit for xfc, extal, xtal 3 3. these pins are internally clamped to v sspll and v ddpll i dl -25 +25 ma 12 instantaneous maximum current single pin limit for test 4 4. this pin is clamped low to v ssr , but not clamped high. this pin must be tied low in applications. i dt -0.25 0 ma 13 operating temperature range (packaged) t a ?40 125 c 14 operating temperature range (junction) t j ?40 140 c 15 storage temperature range t stg ?65 155 c device user guide ?9s12kt256dgv1/d v01.09 86 freescale semiconductor a.1.6 esd protection and latch-up immunity all esd testing is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model. a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. a.1.7 operating conditions this chapter describes the operating conditions of the device. unless otherwise noted those conditions apply to all the following data. table a-2 esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 ohm storage capacitance c 100 pf number of pulse per pin positive negative - - 3 3 machine series resistance r1 0 ohm storage capacitance c 200 pf number of pulse per pin positive negative - - 3 3 latch-up minimum input voltage limit -2.5 v maximum input voltage limit 7.5 v table a-3 esd and latch-up protection characteristics num c rating symbol min max unit 1 c human body model (hbm) v hbm 2000 - v 2 c machine model (mm) v mm 200 - v 3 c charge device model (cdm) v cdm 500 - v 4 c latch-up current at 125 c positive negative i lat +100 -100 - ma 5 c latch-up current at 27 c positive negative i lat +200 -200 - ma device user guide ?9s12kt256dgv1/d v01.09 87 freescale semiconductor note: instead of specifying ambient temperature all parameters are specified for the more meaningful silicon junction temperature. for power dissipation calculations refer to section a.1.8 power dissipation and thermal characteristics . a.1.8 power dissipation and thermal characteristics power dissipation and thermal characteristics are closely related. the user must assure that the maximum operating junction temperature is not exceeded. the average chip-junction temperature (t j ) in c can be obtained from: table a-4 operating conditions rating symbol min typ max unit i/o, regulator and analog supply voltage v dd5 3.15 3.3/5 5.5 v internal logic supply voltage 1 notes : 1. the device contains an internal voltage regulator to generate the logic and pll supply out of the i/o supply. the absolute maximum ratings apply when this regulator is disabled and the device is powered from an external source. v dd 2.35 2.5 2.75 v pll supply voltage (1) v ddpll 2.35 2.5 2.75 v voltage difference vddx to vdda ? vddx -0.1 0 0.1 v voltage difference vssx to vssr and vssa ? vssx -0.1 0 0.1 v oscillator f osc 0.5 - 16 mhz bus frequency f bus 0.5 - 25 mhz mc9s12k-family c/MC9S12KT256c operating junction temperature range t j -40 - 100 c operating ambient temperature range 2 2. please refer to section a.1.8 power dissipation and thermal characteristics for more details about the rela - tion between ambient temperature t a and device junction temperature t j . t a -40 27 85 c mc9s12k-family v/ MC9S12KT256 v operating junction temperature range t j -40 - 120 c operating ambient temperature range (2) t a -40 27 105 c mc9s12k-family m/MC9S12KT256m operating junction temperature range t j -40 - 140 c operating ambient temperature range (2) t a -40 27 125 c t j t a p d ja ? () + = t j junction temperature, [ c ] = t a ambient temperature, [ c ] = device user guide ?9s12kt256dgv1/d v01.09 88 freescale semiconductor the total power dissipation can be calculated from: two cases with internal voltage regulator enabled and disabled must be considered: 1. internal voltage regulator disabled p io is the sum of all output currents on i/o ports associated with vddx and vddr. for r dson is valid: respectively 2. internal voltage regulator enabled i ddr is the current shown in table a-8 and not the overall current flowing into vddr, which additionally contains the current flowing into the external loads with output high. p io is the sum of all output currents on i/o ports associated with vddx and vddr. p d total chip power dissipation, [w] = ja package thermal resistance, [ c/w] = p d p int p io + = p int chip internal power dissipation, [w] = p int i dd v dd ? i ddpll v ddpll ? i dda +v dda ? + = p io r dson i i io i 2 ? = r dson v ol i ol ------------ for outputs driven low ; = r dson v dd5 v oh i oh ------------------------------------ for outputs driven high ; = p int i ddr v ddr ? i dda v dda ? + = p io r dson i i io i 2 ? = device user guide ?9s12kt256dgv1/d v01.09 89 freescale semiconductor a.1.9 i/o characteristics this section describes the characteristics of all 3.3v/5v i/o pins. all parameters are not always applicable, e.g. not all pins feature pull up/down resistances. table a-5 thermal package characteristics 1 notes : 1. the values for thermal resistance are achieved by package simulations num c rating symbol min typ max unit 1 t thermal resistance lqfp112, single sided pcb 2 2. pc board according to eia/jedec standard 51-2 ja - - 54 o c/w 2 t thermal resistance lqfp112, double sided pcb with 2 internal planes 3 3. pc board according to eia/jedec standard 51-7 ja - - 41 o c/w 3 t thermal resistance qfp 80, single sided pcb ja - - 51 o c/w 4 t thermal resistance qfp 80, double sided pcb with 2 internal planes ja - - 41 o c/w device user guide ?9s12kt256dgv1/d v01.09 90 freescale semiconductor table a-6 5v i/o characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 - v dd5 + 0.3 v 2 p input low voltage v il v ss5 - 0.3 - 0.35*v dd5 v 3 c input hysteresis v hys 250 mv 4 p input leakage current (pins in high impedance input mode) v in = v dd5 or v ss5 i in ?.5 - 2.5 a 5 p output high voltage (pins in output mode) partial drive i oh = ?.0ma full drive i oh = ?0.0ma v oh v dd5 ?0.8 - - v 6 p output low voltage (pins in output mode) partial drive i ol = +2.0ma full drive i ol = +10.0ma v ol - - 0.8 v 7 p internal pull up device current, tested at v il max. i pul - - ?30 a 8 p internal pull up device current, tested at v ih min. i puh -10 - - a 9 p internal pull down device current, tested at v ih min. i pdh - - 130 a 10 p internal pull down device current, tested at v il max. i pdl 10 - - a 11 d input capacitance c in 7 - pf 12 t injection current 1 single pin limit total device limit. sum of all injected currents notes : 1. refer to section a.1.4 current injection , for more details i ics i icp -2.5 -25 - 2.5 25 ma 13 p port h, j, p interrupt input pulse ?tered 2 2. parameter only applies in stop or pseudo stop mode. t pign 3 s 14 p port h, j, p interrupt input pulse passed (2) t pval 10 s device user guide ?9s12kt256dgv1/d v01.09 91 freescale semiconductor a.1.10 supply currents this section describes the current consumption characteristics of the device as well as the conditions for the measurements. table a-7 3.3v i/o characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p input high voltage v ih 0.65*v dd5 - v dd5 + 0.3 v 2 p input low voltage v il v ss5 - 0.3 - 0.35*v dd5 v 3 c input hysteresis v hys 250 mv 4 p input leakage current (pins in high impedance input mode) v in = v dd5 or v ss5 i in ? - 1 a 5 p output high voltage (pins in output mode) partial drive i oh = ?.75ma full drive i oh = ?.5ma v oh v dd5 ?0.4 - - v 6 p output low voltage (pins in output mode) partial drive i ol = +0.9ma full drive i ol = +5.5ma v ol - - 0.4 v 7 p internal pull up device current, tested at v il max. i pul - - ?0 a 8 p internal pull up device current, tested at v ih min. i puh -6 - - a 9 p internal pull down device current, tested at v ih min. i pdh - - 60 a 10 p internal pull down device current, tested at v il max. i pdl 6 - - a 11 d input capacitance c in 7 - pf 12 t injection current 1 single pin limit total device limit. sum of all injected currents notes : 1. refer to section a.1.4 current injection , for more details i ics i icp -2.5 -25 - 2.5 25 ma 13 p port p, j interrupt input pulse ?tered 2 2. parameter only applies in stop or pseudo stop mode. t pulse 3 s 14 p port p, j interrupt input pulse passed (2) t pulse 10 s device user guide ?9s12kt256dgv1/d v01.09 92 freescale semiconductor a.1.10.1 measurement conditions all measurements are without output loads. unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25mhz bus frequency using a 4mhz oscillator. a.1.10.2 additional remarks in expanded modes the currents flowing in the system are highly dependent on the load at the address, data and control signals as well as on the duty cycle of those signals. no generally applicable numbers can be given. a very good estimate is to take the single chip currents and add the currents due to the external loads. device user guide ?9s12kt256dgv1/d v01.09 93 freescale semiconductor table a-8 supply current characteristics conditions are shown in table a-4 unless otherwise noted num rating symbol min typ max unit 1 run supply currents single chip, internal regulator enabled i dd5 65 ma 2 wait supply current all modules enabled only rti enabled 1 notes : 1. pll off i ddw 40 5 ma 3 pseudo stop current (rti and cop enabled) 1,2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i ddps 90 130 155 180 250 295 470 520 1000 350 1200 2400 5000 a 4 pseudo stop current (rti and cop disabled) 1,2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c i ddps 40 80 105 130 200 245 420 470 800 200 1000 2000 5000 a 5 stop current 2 -40 c 27 c 70 c 85 c "c" temp option 100 c 105 c "v" temp option 120 c 125 c "m" temp option 140 c 2. all those low power dissipation levels t j = t a can be assumed. i dds 20 60 85 110 180 225 400 450 600 100 800 1800 5000 a device user guide ?9s12kt256dgv1/d v01.09 94 freescale semiconductor a.2 voltage regulator (vreg_3v3) operating characteristics this section describes the characteristics of the on chip voltage regulator. table a-9 vreg_3v3 - operating conditions num c characteristic symbol min typical max unit 1 p input voltages v vddr,a 3.15 ? 5.5 v 2 p regulator current reduced power mode shutdown mode i reg 20 12 50 40 a a 3 p output voltage core full performance mode reduced power mode shutdown mode 1 notes : 1. high impedance output v dd 2.35 1.7 2.5 2.5 2.75 2.75 v v v 4 p output voltage pll full performance mode reduced power mode 2 shutdown mode (1) 2. current iddpll = 500 a v ddpll 2.35 1.7 2.5 2.5 2.75 2.75 v v v 5 p low voltage interrupt 3 assert level deassert level 3. monitors v dda , active only in full performance mode. indicates i/o & adc performance degradation due to low supply voltage. v lvia v lvid 4.1 4.25 4.37 4.52 4.66 4.77 v v 5 p low voltage reset 4 assert level deassert level 4. monitors v dd , active only in full performance mode. v lvra and v pord must overlap v lvra v lvrd 2.25 2.55 v v 7 c power-on reset 5 assert level deassert level 5. monitors v dd . active in all modes. note: the electrical characteristics given in this section are preliminary and should be used as a guide only. values in this section cannot be guaranteed by motorola and are subject to change without notice. v pora v pord 0.97 --- --- 2.05 v v device user guide ?9s12kt256dgv1/d v01.09 95 freescale semiconductor a.3 chip power-up and lvi/lvr graphical explanation voltage regulator sub modules lvi (low voltage interrupt), por (power-on reset) and lvr (low voltage reset) handle chip power-up or drops of the supply voltage. their function is described in figure a-1 . figure a-1 voltage regulator - chip power-up and voltage drops (not scaled) a.4 output loads a.4.1 resistive loads the on-chip voltage regulator is intended to supply the internal logic and oscillator circuits allows no external dc loads. v lvid v lvia v lvrd v lvra v pord lvi por lvr t v v dda v dd lvi enabled lvi disabled due to lvr device user guide ?9s12kt256dgv1/d v01.09 96 freescale semiconductor a.4.2 capacitive loads the capacitive loads are specified in table a-10 . ceramic capacitors with x7r dielectricum are required. table a-10 voltage regulator - capacitive loads num characteristic symbol min typical max unit 1 vdd external capacitive load c ddext 200 440 12000 nf 2 vddpll external capacitive load c ddpllext 90 220 5000 nf device user guide ?9s12kt256dgv1/d v01.09 97 freescale semiconductor a.5 atd characteristics this section describes the characteristics of the analog to digital converter. a.5.1 atd operating characteristics the table a-11 shows conditions under which the atd operates. the following constraints exist to obtain full-scale, full range results: vssa vrl vin vrh vdda . this constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to. if the input level goes outside of this range it will effectively be clipped. table a-11 5v atd operating characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d reference potential low high vrl vrh vssa vdda/2 vdda/2 vdda v v 2 c differential reference voltage 1 notes : 1. full accuracy is not guaranteed when differential voltage is less than 4.75v vrh-vrl 4.75 5.0 5.25 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4 d atd 10-bit conversion period clock cycles 2 conv, time at 2.0mhz atd clock f atdclk conv, time at 4.0mhz 3 atd clock f atdclk 2. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. 3. reduced accuracy see table a-14 and table a-15 . n conv10 t conv10 t conv10 14 7 3.5 28 14 7 cycles s s 5 d atd 8-bit conversion period clock cycles (1) conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles s 6 d stop recovery time (v dda =5.0 volts) t sr 20 s 7 p reference supply current (two atd modules) i ref 0.750 ma 8 p reference supply current (one atd module) i ref 0.375 ma device user guide ?9s12kt256dgv1/d v01.09 98 freescale semiconductor table a-12 3.3v atd operating characteristics a.5.2 factors influencing accuracy three factors - source resistance, source capacitance and current injection - have an influence on the accuracy of the atd. a.5.2.1 source resistance: due to the input pin leakage current as specified in table a-6 and table a-7 in conjunction with the source resistance there will be a voltage drop from the signal source to the atd input. the maximum source resistance r s specifies results in an error of less than 1/2 lsb (2.5mv) at the maximum leakage current. if device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance are allowed. a.5.2.2 source capacitance when sampling an additional internal capacitor is switched to the input. this can cause a voltage drop due to charge sharing with the external and the pin capacitance. for a maximum sampling error of the input voltage 1lsb, then the external filter capacitor, c f 1024 * (c ins - c inn ). a.5.2.3 current injection there are two cases to consider. conditions are shown in table a-4 unless otherwise noted; supply voltage 3.3v-10% <= v dda <= 3.3v+10% num c rating symbol min typ max unit 1 d reference potential low high v rl v rh v ssa v dda /2 v dda /2 v dda v v 2 c differential reference voltage v rh -v rl 3.0 3.3 3.6 v 3 d atd clock frequency f atdclk 0.5 2.0 mhz 4 d atd 10-bit conversion period clock cycles 1 conv, time at 2.0mhz atd clock f atdclk conv, time at 4.0mhz 2 atd clock f atdclk notes : 1. the minimum time assumes a final sample period of 2 atd clocks cycles while the maximum time assumes a final sample period of 16 atd clocks. 2. reduced accuracy see table a-14 and table a-15 . n conv10 t conv10 t conv10 14 7 3.5 28 14 7 cycles s s 5 d atd 8-bit conversion period clock cycles (1) conv, time at 2.0mhz atd clock f atdclk n conv8 t conv8 12 6 26 13 cycles s 6 d recovery time (v dda =3.3 volts) t rec 20 s 7 p reference supply current (two atd modules) i ref 0.500 ma 8 p reference supply current (one atd module) i ref 0.250 ma device user guide ?9s12kt256dgv1/d v01.09 99 freescale semiconductor 1. a current is injected into the channel being converted. the channel being stressed has conversion values of $3ff ($ff in 8-bit mode) for analog inputs greater than vrh and $000 for values less than vrl unless the current is higher than specified as disruptive conditions. 2. current is injected into pins in the neighborhood of the channel being converted. a portion of this current is picked up by the channel (coupling ratio k), this additional current impacts the accuracy of the conversion depending on the source resistance. the additional input voltage error on the converted channel can be calculated as v err = k * r s * i inj , with i inj being the sum of the currents injected into the two pins adjacent to the converted channel. a.5.3 atd accuracy table a-14 and table a-15 specify the atd conversion performance excluding any errors due to current injection, input capacitance and source resistance. table a-13 atd electrical characteristics conditions are shown in table a-4 unless otherwise noted num rating symbol min typ max unit 1 max input source resistance r s - - 1 k ? 2 total input capacitance non sampling sampling c inn c ins 10 22 pf 3 disruptive analog input current i na -2.5 2.5 ma 4 coupling ratio positive current injection k p 10 -4 a/a 5 coupling ratio negative current injection k n 10 -2 a/a table a-14 5v atd conversion performance conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 5.12v. resulting to one 8 bit count = 20mv and one 10 bit count = 5mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 5 mv 2 p 10-bit differential nonlinearity dnl ? 1 counts 3 p 10-bit integral nonlinearity inl ?.5 1.5 2.5 counts 4 p 10-bit absolute error 1 ae -3 2.0 3 counts 5 c 10-bit absolute error at f atdclk = 4mhz ae 7.0 counts 6 p 8-bit resolution lsb 20 mv 7 p 8-bit differential nonlinearity dnl ?.5 0.5 counts 8 p 8-bit integral nonlinearity inl ?.0 0.5 1.0 counts 9 p 8-bit absolute error (1) ae -1.5 1.0 1.5 counts device user guide ?9s12kt256dgv1/d v01.09 100 freescale semiconductor table a-15 3.3v atd conversion performance for the following definitions see also figure a-2 . differential non-linearity (dnl) is defined as the difference between two adjacent switching steps. the integral non-linearity (inl) is defined as the sum of all dnls: notes : 1. these values include quantization error which is inherently 1/2 count for any a/d converter. conditions are shown in table a-4 unless otherwise noted v ref = v rh - v rl = 3.328v. resulting to one 8 bit count = 13mv and one 10 bit count = 3.25mv f atdclk = 2.0mhz num c rating symbol min typ max unit 1 p 10-bit resolution lsb 3.25 mv 2 p 10-bit differential nonlinearity dnl ?.5 1.5 counts 3 p 10-bit integral nonlinearity inl ?.5 1.5 3.5 counts 4 p 10-bit absolute error 1 notes : 1. these values include the quantization error which is inherently 1/2 count for any a/d converter. ae -5 2.5 5 counts 5 c 10-bit absolute error at f atdclk = 4mhz ae 7.0 counts 6 p 8-bit resolution lsb 13 mv 7 p 8-bit differential nonlinearity dnl ?.5 0.5 counts 8 p 8-bit integral nonlinearity inl ?.5 0.1 1.5 counts 9 p 8-bit absolute error (1) ae -2.0 1.5 2.0 counts dnl i () v i v i1 1lsb ------------------------ 1 = inl n () dnl i () i1 = n v n v 0 1lsb ------------------- - n == device user guide ?9s12kt256dgv1/d v01.09 101 freescale semiconductor figure a-2 atd accuracy definitions note: figure a-2 shows only definitions, for specification values refer to table a-14 and table a-15 . 1 5 vin mv 10 15 20 25 30 35 40 5085 5090 5095 5100 5105 5110 5115 5120 5065 5070 5075 5080 5060 0 3 2 5 4 7 6 50 $3f7 $3f9 $3f8 $3fb $3fa $3fd $3fc $3fe $3ff $3f4 $3f6 $3f5 8 9 1 2 $ff $fe $fd $3f3 10-bit resolution 8-bit resolution ideal transfer curve 10-bit transfer curve 8-bit transfer curve 5055 10-bit absolute error boundary 8-bit absolute error boundary lsb v i-1 v i dnl device user guide ?9s12kt256dgv1/d v01.09 102 freescale semiconductor a.6 nvm, flash and eeprom note: unless otherwise noted the abbreviation nvm (non volatile memory) is used for both flash and eeprom. a.6.1 nvm timing the time base for all nvm program or erase operations is derived from the oscillator. a minimum oscillator frequency f nvmosc is required for performing program or erase operations. the nvm modules do not have any means to monitor the frequency and will not prevent program or erase operation at frequencies above or below the specified minimum. attempting to program or erase the nvm modules at a lower frequency a full program or erase transition is not assured. the flash and eeprom program and erase operations are timed using a clock derived from the oscillator using the fclkdiv and eclkdiv registers respectively. the frequency of this clock must be set within the limits specified as f nvmop . the minimum program and erase times shown in table a-16 are calculated for maximum f nvmop and maximum f bus . the maximum times are calculated for minimum f nvmop and a f bus of 2mhz. a.6.1.1 single word programming the programming time for single word programming is dependant on the bus frequency as a well as on the frequency f nvmop and can be calculated according to the following formula. a.6.1.2 row programming flash programming where up to 64 words in a row can be programmed consecutively by keeping the command pipeline filled. the time to program a consecutive word can be calculated as: the time to program a whole row is: row programming is more than 2 times faster than single word programming. a.6.1.3 sector erase erasing a 512 byte flash sector or a 4 byte eeprom sector takes: t swpgm 9 1 f nvmop --------------------- ? 25 1 f bus ---------- ? + = t bwpgm 4 1 f nvmop --------------------- ? 9 1 f bus ---------- ? + = t brpgm t swpgm 63 t bwpgm ? + = device user guide ?9s12kt256dgv1/d v01.09 103 freescale semiconductor the setup time can be ignored for this operation. a.6.1.4 mass erase erasing a nvm block takes: the setup time can be ignored for this operation. a.6.1.5 blank check the time it takes to perform a blank check on the flash or eeprom is dependant on the location of the first non-blank word starting at relative address zero. it takes one bus cycle per word to verify plus a setup of the command. table a-16 nvm timing characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 d external oscillator clock f nvmosc 0.5 50 1 notes : 1. restrictions for oscillator in crystal mode apply! mhz 2 d bus frequency for programming or erase operations f nvmbus 1 mhz 3 d operating frequency f nvmop 150 200 khz 4 p single word programming time t swpgm 46 2 2. minimum programming times are achieved under maximum nvm operating frequency f nvmop and maximum bus frequency f bus . 74.5 3 3. maximum erase and programming times are achieved under particular combinations of f nvmop and bus frequency f bus . refer to formula in sections section a.6.1.1 single word programming - section a.6.1.4 mass erase for guidance. s 5 d flash burst programming consecutive word 4 4. burst programming operations are not applicable to eeprom t bwpgm 20.4 (2) 31 (3) s 6 d flash burst programming time for 64 words (4) t brpgm 1331.2 (2) 2027.5 (3) s 7 p sector erase time t era 20 5 5. minimum erase times are achieved under maximum nvm operating frequency f nvmop . 26.7 (3) ms 8 p mass erase time t mass 100 (5) 133 (3) ms 9 d blank check time flash per block t check 11 6 6. minimum time, if first word in the array is not blank 65546 7 7. maximum time to complete check on an erased block t cyc 10 d blank check time eeprom per block t check 11 (6) 2058 (7) t cyc t era 4000 1 f nvmop --------------------- ? t mass 20000 1 f nvmop --------------------- ? t check location t cyc 10 t cyc ? + ? device user guide ?9s12kt256dgv1/d v01.09 104 freescale semiconductor a.6.2 nvm reliability the reliability of the nvm blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures. the failure rates for data retention and program/erase cycling are specified at the operating conditions noted. the program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed. note: all values shown in table a-17 are target values and subject to further extensive characterization. table a-17 nvm reliability characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 c data retention at an average junction temperature of t javg = 70 c t nvmret 15 years 2 c flash number of program/erase cycles n flpe 1000 10,000 cycles 3 c eeprom number of program/erase cycles (?0 c t j 0 c) n eepe 10,000 cycles 4 c eeprom number of program/erase cycles (0 c < t j 140 c) n eepe 100,000 cycles device user guide ?9s12kt256dgv1/d v01.09 105 freescale semiconductor a.7 reset, oscillator and pll this section summarizes the electrical characteristics of the various startup scenarios for oscillator and phase-locked-loop (pll). a.7.1 startup table a-18 summarizes several startup characteristics explained in this section. detailed description of the startup behavior can be found in the clock and reset generator (crg) block user guide. table a-18 startup characteristics a.7.1.1 por the release level v porr and the assert level v pora are derived from the v dd supply. they are also valid if the device is powered externally. after releasing the por reset the oscillator and the clock quality check are started. if after a time t cqout no valid oscillation is detected, the mcu will start using the internal self clock. the fastest startup time possible is given by n uposc . a.7.1.2 sram data retention provided an appropriate external reset signal is applied to the mcu, preventing the cpu from executing code when vdd5 is out of specification limits, the sram contents integrity is guaranteed if after the reset the porf bit in the crg flags register has not been set. a.7.1.3 external reset when external reset is asserted for a time greater than pw rstl the crg module generates an internal reset, and the cpu starts fetching the reset vector without doing a clock quality check, if there was an oscillation before reset. a.7.1.4 stop recovery out of stop the controller can be woken up by an external interrupt. a clock quality check as after por is performed before releasing the clocks to the system. conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 t por release level v porr 2.07 v 2 t por assert level v pora 0.97 v 3 d reset input pulse width, minimum input time pw rstl 2 t osc 4 d startup from reset n rst 192 196 n osc 5 d interrupt pulse width, irq edge-sensitive mode pw irq 20 ns 6 d wait recovery startup time t wrs 14 t cyc device user guide ?9s12kt256dgv1/d v01.09 106 freescale semiconductor a.7.1.5 pseudo stop and wait recovery the recovery from pseudo stop and wait are essentially the same since the oscillator was not stopped in both modes. the controller can be woken up by internal or external interrupts. after t wrs the cpu starts fetching the interrupt vector. a.7.2 oscillator the device features an internal low-power loop controlled pierce oscillator and a full swing pierce oscillator/external clock mode. the selection of loop controlled pierce oscillator or full swing pierce oscillator/external clock depends on the xclks signal which is sampled during reset. full swing pierce oscillator/external clock mode allows the input of a square wave. before asserting the oscillator to the internal system clocks the quality of the oscillation is checked for each start from either power-on, stop or oscillator fail. t cqout specifies the maximum time before switching to the internal self clock mode after por or stop if a proper oscillation is not detected. the quality check also determines the minimum oscillator start-up time t uposc . the device also features a clock monitor. a clock monitor failure is asserted if the frequency of the incoming clock signal is below the assert frequency f cmfa table a-19 oscillator characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1a c crystal oscillator range (loop controlled pierce) f osc 4.0 16 mhz 1b c crystal oscillator range (full swing pierce) 1 , 2 notes : 1. depending on the crystal a damping series resistor might be necessary f osc 0.5 40 mhz 2 p startup current i osc 100 a 3 c oscillator start-up time (loop controlled pierce) t uposc 3 3 50 4 ms 4 d clock quality check time-out t cqout 0.45 2.5 s 5 p clock monitor failure assert frequency f cmfa 50 100 200 khz 6 p external square wave input frequency 2 f ext 0.5 50 mhz 7 d external square wave pulse width low t extl 9.5 ns 8 d external square wave pulse width high t exth 9.5 ns 9 d external square wave rise time t extr 1 ns 10 d external square wave fall time t extf 1 ns 11 d input capacitance (extal, xtal pins) c in 7 pf 12 p extal pin input high voltage v ih,extal 0.7*v ddpll v t extal pin input high voltage v ih,extal v ddpll + 0.3 v 13 p extal pin input low voltage v il,extal 0.3*v ddpll v t extal pin input low voltage v il,extal v sspll - 0.3 v 14 c extal pin input hysteresis v hys,extal 250 mv device user guide ?9s12kt256dgv1/d v01.09 107 freescale semiconductor a.7.3 phase locked loop the oscillator provides the reference clock for the pll. the pll s voltage controlled oscillator (vco) is also the system clock source in self clock mode. a.7.3.1 xfc component selection this section describes the selection of the xfc components to achieve a good filter characteristics. figure a-3 basic pll functional diagram the following procedure can be used to calculate the resistance and capacitance values using typical values for k 1 , f 1 and i ch from table a-20 . the grey boxes show the calculation for f vco = 50mhz and f ref = 1mhz. e.g., these frequencies are used for f osc = 4mhz and a 25mhz bus clock. the vco gain at the desired vco frequency is approximated by: the phase detector relationship is given by: 2. only valid if full swing pierce oscillator/external clock mode is selected 3. f osc = 4mhz, c = 22pf. 4. maximum value is for extreme cases using high q, low frequency crystals f osc 1 refdv+1 f ref phase detector vco k v 1 synr+1 f vco loop divider k 1 2 ? f cmp c s r c p vddpll xfc pin k v k 1 e f 1 f vco () k 1 1v ? ----------------------- ? = 100 e 60 50 () 100 ----------------------- - ? = = -90.48mhz/v device user guide ?9s12kt256dgv1/d v01.09 108 freescale semiconductor i ch is the current in tracking mode. the loop bandwidth f c should be chosen to fulfill the gardner? stability criteria by at least a factor of 10, typical values are 50. = 0.9 ensures a good transient response. and finally the frequency relationship is defined as with the above values the resistance can be calculated. the example is shown for a loop bandwidth f c =10khz: the capacitance c s can now be calculated as: the capacitance c p should be chosen in the range of: a.7.3.2 jitter information note: this section is under construction the basic functionality of the pll is shown in figure a-3 . with each transition of the clock f cmp , the deviation from the reference clock f ref is measured and input voltage to the vco is adjusted accordingly.the adjustment is done continuously with no abrupt changes in the clock output frequency. noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock jitter. this jitter affects the real minimum and maximum clock periods as illustrated in figure a-4 . k i ch k v ? = = 316.7hz/ ? f c 2 f ref ?? 1 2 + + ?? ?? ? ------------------------------------------ 1 10 ------ f c f ref 410 ? -------------- 0.9 = () ; < < f c < 25khz n f vco f ref ------------- 2 s y n r 1 + () ? == = 50 r 2 nf c ??? k ---------------------------- - = = 2* *50*10khz/(316.7hz/ ? ) =9.9k ? =~10k ? c s 2 2 ? f c r ?? --------------------- - 0.516 f c r ? -------------- - 0.9 = () ; = = 5.19nf =~ 4.7nf c s 20 ? c p c s 10 ? ? c p = 470pf device user guide ?9s12kt256dgv1/d v01.09 109 freescale semiconductor figure a-4 jitter definitions the relative deviation of t nom is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (n). defining the jitter as: note: from the evaluation data a formula for t max = f(n), resp. t min = f(n) should be derived. assuming no long term drift of the reference clock, the following will hold this is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. 2 3 n-1 n 1 0 t nom t max1 t min1 t maxn t minn jn () max 1 t max n () nt nom ? --------------------- 1 t min n () nt nom ? -------------------- - , ?? ?? ?? = jn () n lim 0 = device user guide ?9s12kt256dgv1/d v01.09 110 freescale semiconductor table a-20 pll characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p self clock mode frequency f scm 1 5.5 mhz 2 d vco locking range f vco 8 50 mhz 3 d lock detector transition from acquisition to tracking mode ? trk 3% 4% 1 notes : 1. % deviation from target frequency 4 d lock detection ? lock 0% 1.5% (1) 5 d un-lock detection ? unl 0.5% 2.5% (1) 6 d lock detector transition from tracking to acquisition mode ? unt 6% 8% (1) 7 c pllon total stabilization delay 2 2. f osc = 4mhz, f bus = 25mhz equivalent f vco = 50mhz: refdv = #$03, synr = #$018, cs = 4.7nf, cp = 470pf, rs = 10k ? . t stab 0.5 ms 8 d pllon acquisition mode stabilization delay (2) t acq 0.3 ms 9 d pllon tracking mode stabilization delay (2) t al 0.2 ms 10 d fitting parameter vco loop gain k 1 -100 mhz/v 11 d fitting parameter vco loop frequency f 1 60 mhz 12 d charge pump current acquisition mode i ch -38.5 a 13 d charge pump current tracking mode i ch -3.5 a 14 c jitter ? parameter 1 (2) j 1 1.1 % 15 c jitter ? parameter 2 (2) j 2 0.13 % device user guide ?9s12kt256dgv1/d v01.09 111 freescale semiconductor a.8 mscan table a-21 mscan wake-up pulse characteristics conditions are shown in table a-4 unless otherwise noted num c rating symbol min typ max unit 1 p mscan wake-up dominant pulse ?tered t wup 2 s 2 p mscan wake-up dominant pulse pass t wup 5 s device user guide ?9s12kt256dgv1/d v01.09 112 freescale semiconductor a.9 spi a.9.1 master mode figure a-5 and figure a-6 illustrate the master mode timing. timing values are shown in table a-22 . figure a-5 spi master timing (cpha = 0) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) 1 9 5 6 msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 10 4 4 2 9 (cpol = 0) (cpol = 1) 3 11 12 1.if configured as an output. 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. device user guide ?9s12kt256dgv1/d v01.09 113 freescale semiconductor figure a-6 spi master timing (cpha =1) table a-22 spi master mode timing characteristics conditions are shown in table a-4 unless otherwise noted, cload = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 4 f bus 1 p sck period t sck 4 2048 t bus 2 d enable lead time t lead 1 / 2 t sck 3 d enable lag time t lag 1 / 2 t sck 4 d clock (sck) high or low time t wsck t bus ? 30 1024 t bus ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 0 ns 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0 ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns sck (output) sck (output) miso (input) mosi (output) 1 5 6 msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 4 4 9 11 12 10 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 2 12 11 3 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. device user guide ?9s12kt256dgv1/d v01.09 114 freescale semiconductor a.9.2 slave mode figure a-7 and figure a-8 illustrate the slave mode timing. timing values are shown in table a-23 . figure a-7 spi slave timing (cpha = 0) figure a-8 spi slave timing (cpha =1) sck (input) sck (input) mosi (input) miso (output) ss (input) 1 9 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 10 4 4 2 7 (cpol = 0) (cpol = 1) 3 12 note: not defined but normally msb of character just received. slave 12 11 10 see 11 note 8 sck (input) sck (input) mosi (input) miso (output) 1 5 6 msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 4 4 9 11 12 10 see (cpol = 0) (cpol = 1) ss (input) 2 12 11 3 note: not defined but normally lsb of character just received. slave note 7 8 device user guide ?9s12kt256dgv1/d v01.09 115 freescale semiconductor table a-23 spi slave mode timing characteristics conditions are shown in table a-4 unless otherwise noted, cload = 200pf on all outputs num c rating symbol min typ max unit 1 p operating frequency f op dc 1 / 4 f bus 1 p sck period t sck 4 2048 t bus 2 d enable lead time t lead 1 t cyc 3 d enable lag time t lag 1 t cyc 4 d clock (sck) high or low time t wsck t cyc ? 30 ns 5 d data setup time (inputs) t su 25 ns 6 d data hold time (inputs) t hi 25 ns 7 d slave access time t a 1 t cyc 8 d slave miso disable time t dis 1 t cyc 9 d data valid (after sck edge) t v 25 ns 10 d data hold time (outputs) t ho 0 ns 11 d rise time inputs and outputs t r 25 ns 12 d fall time inputs and outputs t f 25 ns device user guide ?9s12kt256dgv1/d v01.09 116 freescale semiconductor a.10 external bus timing a timing diagram of the external multiplexed-bus is illustrated in figure a-9 with the actual timing values shown on table table a-24 . all major bus signals are included in the diagram. while both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle. a.10.1 general muxed bus timing the expanded bus timings are highly dependent on the load conditions. the timing parameters shown assume a balanced load across all outputs. device user guide ?9s12kt256dgv1/d v01.09 117 freescale semiconductor figure a-9 general external bus timing addr/data (read) addr/data (write) addr data data 5 10 11 8 16 6 eclk 1, 2 3 4 addr data data 12 15 9 7 14 13 ecs 21 20 22 23 non-multiplexed 17 19 lstrb 29 no a cc 32 pipo0 pipo1, pe6,5 35 18 27 28 30 33 36 31 34 r/ w 24 26 25 addresses pe4 pa, pb pa, pb pk5:0 pk7 pe2 pe3 pe7 device user guide ?9s12kt256dgv1/d v01.09 118 freescale semiconductor table a-24 expanded bus timing characteristics conditions are shown in table a-4 unless otherwise noted, c load = 50pf num c rating symbol min typ max unit 1 p frequency of operation (e-clock) f o 0 25.0 1 2 p cycle time t cyc 40 2 3 d pulse width, e low pw el 17 3 4 d pulse width, e high 1 pw eh 17 4 5 d address delay time t ad 8 5 6 d address valid time to e rise (pw el ? ad ) t av 11 6 7 d muxed address hold time t mah 2 7 8 d address hold to data valid t ahds 7 8 9 d data hold to address t dha 2 9 10 d read data setup time t dsr 13 10 11 d read data hold time t dhr 0 11 12 d write data delay time t ddw 7 12 13 d write data hold time t dhw 2 13 14 d write data setup time (1) (pw eh ? ddw ) t dsw 10 14 15 d address access time (1) (t cyc ? ad ? dsr ) t acca 19 15 16 d e high access time (1) (pw eh ? dsr ) t acce 4 16 17 d non-multiplexed address delay time t nad 7 17 18 d non-muxed address valid to e rise (pw el ? nad ) t nav 10 18 19 d non-multiplexed address hold time t nah 2 19 20 d chip select delay time t csd 16 20 21 d chip select access time (1) (t cyc ? csd ? dsr ) t accs 11 21 22 d chip select hold time t csh 2 22 23 d chip select negated time t csn 8 23 24 d read/write delay time t rwd 7 24 25 d read/write valid time to e rise (pw el ? rwd ) t rwv 10 25 26 d read/write hold time t rwh 2 26 27 d low strobe delay time t lsd 7 27 28 d low strobe valid time to e rise (pw el ? lsd ) t lsv 10 28 29 d low strobe hold time t lsh 2 29 30 d noacc strobe delay time t nod 7 30 31 d noacc valid time to e rise (pw el ? lsd ) t nov 10 31 device user guide ?9s12kt256dgv1/d v01.09 119 freescale semiconductor 32 d noacc hold time t noh 2 32 33 d pipo0 delay time t p0d 2 7 33 34 d pipo0 valid time to e rise (pw el ? p0d ) t p0v 10 34 35 d pipo1 delay time (1) (pw eh -t p1v ) t p1d 2 7 35 36 d pipo1 valid time to e fall t p1v 10 36 notes : 1. affected by clock stretch: add n x t cyc where n=0,1,2 or 3, depending on the number of clock stretches. table a-24 expanded bus timing characteristics conditions are shown in table a-4 unless otherwise noted, c load = 50pf device user guide ?9s12kt256dgv1/d v01.09 120 freescale semiconductor device user guide ?9s12kt256dgv1/d v01.09 121 freescale semiconductor appendix b package information this section provides the physical dimensions of the mc9s12k-family packages. device user guide ?9s12kt256dgv1/d v01.09 122 freescale semiconductor b.1 80-pin qfp package figure b-1 80-pin qfp mechanical dimensions (case no. 841b) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums -a-, -b- and -d- to be determined at datum plane -h-. 5. dimensions s and v to be determined at seating plane -c-. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b-b 61 60 detail a l 41 40 80 -a- l -d- a s a-b m 0.20 d s h 0.05 a-b s 120 21 -b- b v j f n d view rotated 90 detail a b b p -a-,-b-,-d- e h g m m detail c seating plane -c- c datum plane 0.10 -h- datum plane -h- u t r q k w x detail c dim min max millimeters a 13.90 14.10 b 13.90 14.10 c 2.15 2.45 d 0.22 0.38 e 2.00 2.40 f 0.22 0.33 g 0.65 bsc h --- 0.25 j 0.13 0.23 k 0.65 0.95 l 12.35 ref m 5 10 n 0.13 0.17 p 0.325 bsc q 0 7 r 0.13 0.30 s 16.95 17.45 t 0.13 --- u 0 --- v 16.95 17.45 w 0.35 0.45 x 1.6 ref s a-b m 0.20 d s c s a-b m 0.20 d s h 0.05 d s a-b m 0.20 d s c s a-b m 0.20 d s c device user guide ?9s12kt256dgv1/d v01.09 123 freescale semiconductor b.2 100-pin lqfp package figure b-2 100-pin lqfp mechanical dimensions (case no. 983) ? ? ? ? ?? 14.00 bsc millimeters a1 7.00 bsc b 14.00 bsc b1 7.00 bsc c 1.70 c1 0.05 0.20 c2 1.30 1.50 d 0.10 0.30 e 0.45 0.75 f 0.15 0.23 g 0.50 bsc j 0.07 0.20 k 0.50 ref r1 0.08 0.20 s 16.00 bsc s1 8.00 bsc u 0.09 0.16 v 16.00 bsc v1 8.00 bsc w 0.20 ref z 1.00 ref 0 7 0 12 ref notes: 1. dimensions and tolerances per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at the seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.35. minimum space between protrusion and adjacent lead or protrusion 0.07. 1 2 3 view y 4x 25 tips 4x 25 100 76 75 51 26 50 1 view aa c n 0.2 t l? 0.08 t c2 c1 (k) (z) (w) gage plane view aa view y ab plating u j d f rotated 90 clockwise base metal section ab?b 0.05 e 0.25 c l l? m 0.08 n t 3x 3 4x 1 2x r r1 x = l, m or n g a s a1 s1 b1 v1 b v n 0.2 t l? m n t seating 2 4x 100x plane x ab l 12 ref device user guide ?9s12kt256dgv1/d v01.09 124 freescale semiconductor b.3 112-pin lqfp package figure b-3 112-pin lqfp mechanical dimensions (case no. 987) dim a min max 20.000 bsc millimeters a1 10.000 bsc b 20.000 bsc b1 10.000 bsc c --- 1.600 c1 0.050 0.150 c2 1.350 1.450 d 0.270 0.370 e 0.450 0.750 f 0.270 0.330 g 0.650 bsc j 0.090 0.170 k 0.500 ref p 0.325 bsc r1 0.100 0.200 r2 0.100 0.200 s 22.000 bsc s1 11.000 bsc v 22.000 bsc v1 11.000 bsc y 0.250 ref z 1.000 ref aa 0.090 0.160 11 11 13 7 13 view y l-m 0.20 n t 4x 4x 28 tips pin 1 ident 1 112 85 84 28 57 29 56 b v v1 b1 a1 s1 a s view ab 0.10 3 c c2 2 0.050 seating plane gage plane 1 view ab c1 (z) (y) e (k) r2 r1 0.25 j1 view y j1 p g 108x 4x section j1-j1 base rotated 90 counterclockwise metal j aa f d l-m m 0.13 n t 1 2 3 c l l-m 0.20 n t l n m t t 112x x x=l, m or n r r notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. datums l, m and n to be determined at seating plane, datum t. 4. dimensions s and v to be determined at seating plane, datum t. 5. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 per side. dimensions a and b include mold mismatch. 6. dimension d does not include dambar 8 3 0 device user guide ?9s12kt256dgv1/d v01.09 125 freescale semiconductor 9s12kt256dgv1/d v01.09, 9 sep 2004 how to reach us: usa/europe/locations not listed: freescale semiconductor literature distribution p.o. box 5405, denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: freescale semiconductor japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/paci?: freescale semiconductor h.k. ltd. 2 dai king street tai po industrial estate tai po, n.t. hong kong 852-26668334 learn more: for more information about freescale semiconductor products, please visit http://www.freescale.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and speci?ally disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters which may be provided in freescale semiconductor data sheets and/or speci?ations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?ypicals?must be validated for each customer application by customer s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ?freescale semiconductor, inc. 2004. final page of 126 pages |
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